SAM9261 Atmel Corporation, SAM9261 Datasheet - Page 111
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SAM9261
Manufacturer Part Number
SAM9261
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9260.pdf
(290 pages)
2.SAM9261.pdf
(248 pages)
3.SAM9261.pdf
(749 pages)
4.SAM9261.pdf
(44 pages)
5.SAM9261.pdf
(1274 pages)
6.SAM9261.pdf
(43 pages)
Specifications of SAM9261
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
240 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
96
Ext Interrupts
96
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
1
Uart
4
Ssc
3
Sd / Emmc
1
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
No
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
160
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.08 to 1.32
Fpu
No
Mpu / Mmu
No/Yes
Timers
3
Output Compare Channels
3
Input Capture Channels
3
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9260 PDF datasheet
- SAM9261 PDF datasheet #2
- SAM9261 PDF datasheet #3
- SAM9261 PDF datasheet #4
- SAM9261 PDF datasheet #5
- SAM9261 PDF datasheet #6
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- Download datasheet (5Mb)
5.2
5.2.1
5.2.2
5.2.3
ARM DDI 0165B
Hardware interface
Generating an interrupt
Synchronization
Re-enabling interrupts after an interrupt exception
The hardware interrupt is described under the following headings:
•
•
•
•
You can make the ARM9E-S take the FIQ or IRQ exceptions (if interrupts are enabled
within the core) by asserting (LOW) the nFIQ or nIRQ inputs, respectively.
It is essential that once asserted, the interrupt input remains asserted until the ARM9E-S
has completed its interrupt exception entry sequence. When an interrupt input is
asserted, it must remain asserted until the ARM9E-S acknowledges to the source of the
interrupt that the interrupt has been taken. This acknowledgement normally occurs
when the interrupt service routine accesses the peripheral causing the interrupt, for
example:
•
•
•
The nFIQ and nIRQ inputs are synchronous inputs to the ARM9E-S, and must be setup
and held about the rising edge of the ARM9E-S clock, CLK. If interrupt events that are
asynchronous to CLK are present in a system, synchronization register(s) that are
external to the ARM9E-S are required.
You must take care when re-enabling interrupts (for example at the end of an interrupt
routine or with a reentrant interrupt handler). You must ensure that the original source
of the interrupt has been removed before interrupts are enabled again on the ARM9E-S.
If you cannot guarantee this, the ARM9E-S might retake the interrupt exception
prematurely.
When considering the timing relation of removing the source of interrupt and
re-enabling interrupts on the ARM9E-S, you must take into account the pipelined
nature of the ARM9E-S and the memory system to which it is connected. For example,
the instruction that causes the removal of the interrupt request (that is, deassertion of
Generating an interrupt
Synchronization
Re-enabling interrupts after an interrupt exception
Interrupt registers on page 5-5.
by reading an interrupt status register in the systems interrupt controller
by writing to a clear interrupt control bit
by writing data to, or reading data from the interrupting peripheral.
Copyright © 2000 ARM Limited. All rights reserved.
Interrupts
5-3
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