SAM9G45 Atmel Corporation, SAM9G45 Datasheet
SAM9G45
Specifications of SAM9G45
Related parts for SAM9G45
SAM9G45 Summary of contents
Page 1
... Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os with Schmitt trigger input • Package – 324-ball TFBGA, pitch 0.8 mm AT91SAM ARM-based Embedded MPU SAM9G45 Summary NOTE: This is a summary document. The complete document is available on the Atmel website at www.atmel.com. 6438GS–ATARM–13-Jul-11 ...
Page 2
... LCD Controller, resistive touch- screen, camera interface, audio, Ethernet 10/100 and high speed USB and SDIO. With the pro- cessor running at 400MHz and multiple 100+ Mbps data rate peripherals, the SAM9G45 has the performance and bandwidth to the network or local storage media to provide an adequate user experience ...
Page 3
... Block Diagram Figure 2-1. SAM9G45 Block Diagram 6438GS–ATARM–13-Jul-11 PIO SAM9G45 3 ...
Page 4
... XOUT Main Oscillator Output XIN32 Slow Clock Oscillator Input XOUT32 Slow Clock Oscillator Output VBG Bias Voltage Reference for USB PCK0 - PCK1 Programmable Clock Output SAM9G45 4 gives details on the signal names classified by peripheral. Active Type Level Power Supplies Power Power Power ...
Page 5
... Input Debug Unit - DBGU Input Output Advanced Interrupt Controller - AIC Input Input PIO Controller - PIOA- PIOB - PIOC - PIOD - PIOE I/O I/O SAM9G45 Reference Voltage Comments Driven at 0V only. 0: The device is in backup mode VDDBU 1: The device is running (not in backup mode). Accept between 0V and VDDBU VDDBU ...
Page 6
... NWR0 - NWR3 Write Signal NRD Read Signal NWE Write Enable NBS0 - NBS3 Byte Mask Signal CFCE1 - CFCE2 CompactFlash Chip Enable CFOE CompactFlash Output Enable CFWE CompactFlash Write Enable CFIOR CompactFlash IO Read SAM9G45 6 Active Reference Type Level (1) I/O (1) I/O (1) I/O I/O VDDIOM0 Output VDDIOM0 Output ...
Page 7
... Output Low Output Output Output High Speed Multimedia Card Interface - HSMCIx I/O I/O I/O I/O Output Input Output Input Synchronous Serial Controller - SSCx Output Input I/O I/O I/O I/O SAM9G45 Reference Voltage Comments VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 (1) (1) ...
Page 8
... USB Host Port B High Speed Data - DFSDM USB Device Full Speed Data - DFSDP USB Device Full Speed Data + DHSDM USB Device High Speed Data - DHSDP USB Device High Speed Data + SAM9G45 8 Active Type Level AC97 Controller - AC97C Input Output Output Input ...
Page 9
... LCD Controller - LCDC Output Output Output Output Output Output Output Output Touch Screen Analog-to-Digital Converter Analog Analog Analog SAM9G45 Reference Voltage Comments (1) MII only, REFCK in RMII (1) MII only (1) (1) ETX0-ETX1 only in RMII (1) MII only (1) RXDV in MII, CRSDV in RMII ...
Page 10
... I/O lines default as inputs with pull-up resistors enabled, except those which are multiplexed with the External Bus Inter- face signals that require to be enabled as Peripheral at reset. This is explicitly indicated in the column “Reset State” of the peripheral multiplexing tables. SAM9G45 10 Active Reference ...
Page 11
... Package and Pinout The SAM9G45 is delivered in a 324-ball TFBGA package. 4.1 Mechanical Overview of the 324-ball TFBGA Package Figure 4-1 Figure 4-1. 6438GS–ATARM–13-Jul-11 shows the orientation of the 324-ball TFBGA Package Orientation of the 324-ball TFBGA Package ...
Page 12
... TFBGA Package Pinout Table 4-1. SAM9G45 Pinout for 324-ball BGA Package Pin Signal Name Pin A1 PC27 E10 A2 PC28 E11 A3 PC25 E12 A4 PC20 E13 A5 PC12 E14 A6 PC7 E15 A7 PC5 E16 A8 PC0 E17 A9 NWR3/NBS3 E18 A10 NCS0 F1 A11 DQS0 F2 A12 RAS F3 A13 SDCK ...
Page 13
... Table 4-1. SAM9G45 Pinout for 324-ball BGA Package (Continued) Pin Signal Name Pin C13 D10 H4 C14 D6 H5 C15 D2 H6 C16 GNDIOM H7 C17 A18 H8 C18 A12 H9 D1 XOUT32 H10 D2 PD20 H11 D3 GNDBU H12 D4 VDDBU H13 D5 PC24 H14 D6 PC18 H15 D7 PC13 H16 D8 PC6 H17 ...
Page 14
... Power Considerations 5.1 Power Supplies The SAM9G45 has several types of power supply pins: • VDDCORE pins: Power the core, including the processor, the embedded memories and the peripherals; voltage ranges from 0.9V to 1.1V, 1.0V typical. • VDDIOM0 pins: Power the DDR2/LPDDR I/O lines; voltage ranges between 1.65V and 1.95V (1.8V typical). • ...
Page 15
... Separate Address and Data Buses for both the 32-bit instruction interface and the – On Address and Data Buses, data can be 8-bit (Bytes), 16-bit (Half-words) or 32-bit • TCM Interface 6438GS–ATARM–13-Jul-11 each quarter of the page system flexibility 32-bit data interface (Words) SAM9G45 15 ...
Page 16
... Allows Handling of Dynamic Exception Vectors 6.2.1 Matrix Masters The Bus Matrix of the SAM9G45 manages Masters, thus each master can perform an access concurrently with others, depending on whether the slave it accesses is available. Each Master has its own decoder, which can be defined specifically for each master. In order to simplify the addressing, all the masters have the same decodings ...
Page 17
... The remaining masters share DDR Port 2 and DDR Port 3. 6438GS–ATARM–13-Jul-11 List of Bus Matrix Slaves Internal SRAM Internal ROM USB OHCI USB EHCI UDP High Speed RAM LCD User Interface DDR Port 0 DDR Port 1 DDR Port 2 DDR Port 3 External Bus Interface Internal Peripherals SAM9G45 17 ...
Page 18
... Figure 6-1. Table 6-3. SAM9G45 Masters to Slaves Access DDRMP_DIS = 0 Master 0 ARM ARM Slave 926 Instr. 926 Data 0 Internal SRAM 0 X Internal ROM X UHP OHCI X UHP EHCI X LCD User Int. X UDPHS RAM X 1 Reserved X 2 DDR Port DDR Port DDR Port DDR Port 3 ...
Page 19
... Table 6-4. SAM9G45 Masters to Slaves Access with DDRMP_DIS = 1 (default) Master 0 ARM Slave 926 Instr. 926 Data 0 Internal SRAM 0 X Internal ROM X UHP OHCI X UHP EHCI X 1 LCD User Int. X UDPHS RAM X Reserved X 2 DDR Port DDR Port DDR Port ...
Page 20
... SSC1 SSC0 6.4 USB The SAM9G45 features USB communication ports as follows: • 2 Ports USB Host full speed OHCI and High speed EHCI • 1 Device High speed USB Host Port A is directly connected to the first UTMI transceiver. The Host Port B is multiplexed with the USB device High speed and connected to the second UTMI port ...
Page 21
... SSC1 AC97C AC97C MCI1 6438GS–ATARM–13-Jul-11 USB Selection HS HS Transceiver Transceiver EHCI FS OHCI DMA DMA Channel Definition DMA Channel HW T/R interface Number TX/ TX/RX 13 SAM9G45 EN_UDPHS 1 HS USB DMA 21 ...
Page 22
... Two Independent Registers: Debug Control Register and Debug Status Register – Test Access Port Accessible through JTAG Protocol – Debug Communications Channel • Debug Unit – Two-pin UART – Debug Communication Channel Interrupt Handling – Chip ID Register • IEEE1149.1 JTAG Boundary-scan on All Digital Pins. SAM9G45 22 6438GS–ATARM–13-Jul-11 ...
Page 23
... Memories Figure 7-1. SAM9G45 Memory Mapping Address Memory Space 0x00000000 Internal Memories 0x10000000 EBI Chip Select 0 0x20000000 EBI Chip Select 1 DDRSDRC1 0x30000000 EBI Chip Select 2 0x40000000 EBI Chip Select 3 NANDFlash 0x50000000 EBI Chip Select 4 Compact Flash Slot 0 0x60000000 EBI Chip Select 5 Compact Flash Slot 1 ...
Page 24
... Internal SRAM The SAM9G45 product embeds a total of 64 Kbytes high-speed SRAM split in 4 blocks of 16 KBytes connected to one slave of the matrix. After reset and until the Remap Command is per- formed, the four SRAM blocks are contiguous and only accessible at address 0x00300000. After Remap, the SRAM also becomes available at address 0x0 ...
Page 25
... Note: All the memory blocks can always be seen at their specified base addresses that are not concerned by these parameters. The SAM9G45 Bus Matrix manages a boot memory that depends on the level on the pin BMS at reset. The internal memory area mapped between address 0x0 and 0x000F FFFF is reserved to this effect ...
Page 26
... Switch the main clock to the new value 7.3 External Memories The SAM9G45 features a Multi-port DDR2 Interface and an External Bus Interface allowing to connect to a wide range of external memories and to any parallel peripheral. 7.3.1 DDRSDRC0 Multi-port DDRSDR Controller Four AHB Interfaces, Management of All Accesses Maximizes Memory Bandwidth and Mini- mizes Transaction Latency. • ...
Page 27
... Asynchronous read in Page Mode supported ( 32-byte page size) • Multiple device adaptability – Control signals programmable setup, pulse and hold time for each Memory Bank • Multiple Wait State Management – Programmable Wait State Generation 6438GS–ATARM–13-Jul-11 Average Latency of Transactions) SAM9G45 TM M support 27 ...
Page 28
... ECC value available in a register • Automatic Hamming Code Calculation while reading – Error Report, including error flag, correctable error flag and word address being – Support 8- or 16-bit NAND Flash devices with 512-, 1024-, 2048- or 4096-bytes SAM9G45 28 Average Latency of Transactions) detected erroneous pages 6438GS– ...
Page 29
... All the registers of the System Controller can be addressed from a single pointer by using the standard ARM instruction set, as the Load/Store instruction have an indexing mode of ±4 KB. Figure 8-1 on page 30 Figure 7-1 on page 23 peripherals. 6438GS–ATARM–13-Jul-11 shows the System Controller block diagram. shows the mapping of the User Interfaces of the System Controller SAM9G45 29 ...
Page 30
... System Controller Block Diagram Figure 8-1. SAM9G45 System Controller Block Diagram periph_irq[2..24] pit_irq rtt_irq wdt_irq dbgu_irq pmc_irq rstc_irq periph_nreset dbgu_rxd periph_nreset proc_nreset NRST VDDCORE POR VDDBU VDDBU POR backup_nreset backup_nreset SHDN WKUP RC OSC SLOW XIN32 CLOCK XOUT32 OSC XIN 12MHz MAIN OSC ...
Page 31
... MHz input, the only limitation being the lowest input frequency shall be higher or equal to 2 MHz. The USB Device and Host HS Clocks are provided by a the dedicated UTMI PLL (UPLL) embedded in the UTMI macro. 6438GS–ATARM–13-Jul-11 SAM9G45 31 ...
Page 32
... Figure 8-2. 8.6 Slow Clock Selection The SAM9G45 slow clock can be generated either by an external 32768Hz crystal or the on-chip RC oscillator. The 32768 Hz crystal oscillator can be bypassed, by setting the bit OSC32BYP, to accept an external slow clock on XIN32. The internal RC oscillator and the 32768 Hz oscillator can be enabled by setting to 1 respec- tively RCEN bit and OSC32EN bit in the system controller user interface ...
Page 33
... Enable the internal RC oscillator by setting the bit RCEN to 1. • Wait internal RC Startup Time for clock stabilization (software loop). 6438GS–ATARM–13-Jul-11 Slow Clock Clock Generator On Chip RC OSC Slow Clock XIN32 Oscillator XOUT32 SAM9G45 RCEN Slow Clock SLCK OSCSEL OSC32EN OSC32BYP 33 ...
Page 34
... Standby Mode, mix of Idle and Backup Mode, peripheral running at low frequency, processor stopped waiting for an interrupt • Backup Mode, Main Power Supplies off, VDDBU powered by a battery SAM9G45 34 DDR system clock is not available when Master Clock (MCK) equals Processor Clock (PCK). ...
Page 35
... Full Speed OHCI input clock is UPLLCK, USBDIV is 9 (division by 10) • System Input clock is UPLLCK, Prescaler is 2, PCK is 240 MHz • MDIV is ‘01’, MCK is 120 MHz • Only LP-DDR can be used 120 MHz 6438GS–ATARM–13-Jul-11 SAM9G45 Power Management Controller Block Diagram USBS USBDIV+1 /1,/2 UPLLCK Prescaler /1,/2,/4, ...
Page 36
... Thirty-two individually maskable and vectored interrupt sources – Source 0 is reserved for the Fast Interrupt Input (FIQ) – Source 1 is reserved for system peripherals (PIT, RTT, PMC, DBGU, etc.) – Programmable Edge-triggered or Level-sensitive Internal Sources – Programmable Positive/Negative Edge-triggered or High/Low Level-sensitive SAM9G45 36 Controller 6438GS–ATARM–13-Jul-11 ...
Page 37
... Debug Communication Channel Support – Offers visibility of and interrupt trigger from COMMRX and COMMTX signals from 8.15 Chip Identification The SAM9G45 Chip ID is defined in the Debug Unit Chip ID Register and Debug Unit Chip ID Extension Register. • Chip ID: 0x819B05A2 • Ext ID: 0x00000004 • ...
Page 38
... Multi-drive option enables driving in open drain – Programmable pull up on each I/O line – Pin data status register, supplies visibility of the level on the pin at any time • Synchronous output, provides Set and Clear of several I/O lines in a single write SAM9G45 38 6438GS–ATARM–13-Jul-11 ...
Page 39
... Reserved 31 AIC 6438GS–ATARM–13-Jul-11 Figure 7-1, the Peripherals are mapped in the upper 256 Mbytes of the address defines the Peripheral Identifiers of the SAM9G45. A peripheral identifier is required Peripheral Name Advanced Interrupt Controller System Controller Interrupt Parallel I/O Controller A, Parallel I/O Controller B Parallel I/O Controller C Parallel I/O Controller D/E ...
Page 40
... Peripheral ID. However, there is no clock control associated with these peripheral IDs. 9.4 Peripheral Signals Multiplexing on I/O Lines The SAM9G45 features 5 PIO controllers, PIOA, PIOB, PIOC, PIOD and PIOE, which multi- plexes the I/O lines of the peripheral set. Each PIO Controller controls lines. Each line can be assigned to one of two peripheral functions The multiplexing tables in the following paragraphs define how the I/O lines of the peripherals A and B are multiplexed on the PIO Controllers. The two columns “ ...
Page 41
... ETX3 I/O VDDIOP0 ERX2 I/O VDDIOP0 ERX3 I/O VDDIOP0 I/O VDDIOP0 I/O VDDIOP0 I/O VDDIOP0 I/O VDDIOP0 I/O VDDIOP0 I/O VDDIOP0 I/O VDDIOP0 I/O VDDIOP0 I/O VDDIOP0 I/O VDDIOP0 I/O VDDIOP0 I/O VDDIOP0 SCK3 I/O VDDIOP0 RTS3 I/O VDDIOP0 CTS3 I/O VDDIOP0 PWM3 I/O VDDIOP0 TIOB2 I/O VDDIOP0 ETXER I/O VDDIOP0 ERXCK I/O VDDIOP0 ECRS I/O VDDIOP0 ECOL I/O VDDIOP0 PCK0 I/O VDDIOP0 SAM9G45 Function Comments 41 ...
Page 42
... TXD0 PB20 ISI_D0 PB21 ISI_D1 PB22 ISI_D2 PB23 ISI_D3 PB24 ISI_D4 PB25 ISI_D5 PB26 ISI_D6 PB27 ISI_D7 PB28 ISI_PCK PB29 ISI_VSYNC PB30 ISI_HSYNC PB31 ISI_MCK SAM9G45 42 Reset Power Peripheral B State Supply I/O VDDIOP0 I/O VDDIOP0 I/O VDDIOP0 I/O VDDIOP0 I/O VDDIOP0 I/O VDDIOP0 I/O VDDIOP0 I/O VDDIOP0 ISI_D8 I/O VDDIOP2 ...
Page 43
... A20 VDDIOM1 A21 VDDIOM1 A22 VDDIOM1 A23 VDDIOM1 A24 VDDIOM1 I/O VDDIOM1 RTS2 I/O VDDIOM1 TCLK2 I/O VDDIOM1 CTS2 I/O VDDIOM1 A25 VDDIOM1 I/O VDDIOM1 I/O VDDIOM1 I/O VDDIOM1 I/O VDDIOM1 I/O VDDIOM1 I/O VDDIOM1 I/O VDDIOM1 I/O VDDIOM1 I/O VDDIOM1 I/O VDDIOM1 I/O VDDIOM1 I/O VDDIOM1 I/O VDDIOM1 I/O VDDIOM1 I/O VDDIOM1 I/O VDDIOM1 I/O VDDIOM1 I/O VDDIOM1 I/O VDDIOM1 SAM9G45 Function Comments 43 ...
Page 44
... SPI1_NPCS3 PD20 TIOA0 PD21 TIOA1 PD22 TIOA2 PD23 TCLK0 PD24 SPI0_NPCS1 PD25 SPI0_NPCS2 PD26 PCK0 PD27 PCK1 PD28 TSADTRG PD29 TCLK1 TIOB0 PD30 PD31 TIOB1 SAM9G45 44 Reset Power Peripheral B State Supply PWM3 I/O VDDIOP0 I/O VDDIOP0 I/O VDDIOP0 I/O VDDIOP0 I/O VDDIOP0 I/O VDDIOP0 I/O VDDIOP0 TIOA5 I/O VDDIOP0 ...
Page 45
... LCDD5 I/O VDDIOP1 LCDD6 I/O VDDIOP1 LCDD7 I/O VDDIOP1 LCDD10 I/O VDDIOP1 LCDD11 I/O VDDIOP1 LCDD12 I/O VDDIOP1 LCDD13 I/O VDDIOP1 LCDD14 I/O VDDIOP1 LCDD15 I/O VDDIOP1 LCDD18 I/O VDDIOP1 LCDD19 I/O VDDIOP1 LCDD20 I/O VDDIOP1 LCDD21 I/O VDDIOP1 LCDD22 I/O VDDIOP1 LCDD23 I/O VDDIOP1 I/O VDDIOP1 I/O VDDIOP1 I/O VDDIOP1 I/O VDDIOP1 I/O VDDIOP1 I/O VDDIOP1 PCK1 I/O VDDIOP1 SAM9G45 Function Comments 45 ...
Page 46
... Asynchronous Mode stop bits in Synchronous Mode – Parity generation and error detection – Framing error detection, overrun error detection – MSB- or LSB-first SAM9G45 46 peripherals Sensors and data per chip select ...
Page 47
... Variable sampling rate AC97 Codec Interface (48KHz and below) 10.6 Timer Counter (TC) • Three 16-bit Timer Counter Channels • Wide range of functions including: – Frequency Measurement – Event Counting – Interval Measurement – Pulse Generation 6438GS–ATARM–13-Jul-11 SAM9G45 2 S, TDM Buses, Magnetic Card Reader,...) 47 ...
Page 48
... Root Hub Integrated with 2 Downstream USB Ports • Shared Embedded USB Transceivers 10.10 USB High Speed Device Port (UDPHS) • USB V2.0 high-speed compliant, 480 MBits per second • Embedded USB V2.0 UTMI+ high-speed transceiver shared with UHP HS. SAM9G45 48 6438GS–ATARM–13-Jul-11 ...
Page 49
... Automatic wakeup on trigger and back to sleep mode after conversions of all 10.13 Ethernet 10/100 MAC (EMAC) • Compatibility with IEEE Standard 802.3 • 10 and 100 MBits per second data throughput capability • Full- and half-duplex operations 6438GS–ATARM–13-Jul-11 enabled channels SAM9G45 49 ...
Page 50
... User enabled auto-reloading of source, destination and control registers from initially – Auto-loading of source, destination and control registers from system memory at end – Unaligned system address to data transfer width supported in hardware • Channel Buffering SAM9G45 50 lists transfer. Writing a stream of data into non-contiguous fields in system memory ...
Page 51
... Passed Diehard Random Tests Suite • Provides a 32-bit Random Number Every 84 Clock Cycles • For 133 MHz Clock Frequency, Throughput Close to 50 Mbits/s 6438GS–ATARM–13-Jul-11 to control the flow of a DMA transfer in place of a hardware handshaking interface completion, Single/Multiple transaction completion or Error condition SAM9G45 51 ...
Page 52
... Mechanical Characteristics 11.1 Package Drawings Figure 11-1. 324-ball TFBGA Package Drawing SAM9G45 52 6438GS–ATARM–13-Jul-11 ...
Page 53
... SAM9G45 Ordering Information Table 12-1. AT91SAM9G45 Ordering Information Ordering Code AT91SAM9G45-CU 6438GS–ATARM–13-Jul-11 Package Package Type TFBGA324 Green SAM9G45 Temperature Operating Range Industrial -40°C to 85°C 53 ...
Page 54
... Section 10.16 “True Random Number Generator (TRNG)” 1st Page/headers & footers: (text where found) Product Line/Product naming convention changed - AT91SAM ARM-based MPU / SAM9G45 Section 5.1 “Power Supplies”, replaced ground pin names by GNDIOM, GNDCORE, GNDANA, GNDIOP, 6438FS GNDBU, GNDOSC, GNDUTMI ...
Page 55
... Atmel Corporation. All rights reserved. Atmel®, Atmel logo and combinations thereof, DataFlash®, SAM-BA® and others are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. ARM®, the ARMPowered® logo, Thumb® and others are the registered trademarks or trademarks of ARM Ltd. Windows® ...