SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 157
SAM9RL64
Manufacturer Part Number
SAM9RL64
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.SAM9260.pdf
(290 pages)
3.SAM9261.pdf
(248 pages)
4.SAM9R64.pdf
(903 pages)
5.SAM9R64.pdf
(52 pages)
Specifications of SAM9RL64
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
240 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
118
Ext Interrupts
118
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device
Spi
1
Twi (i2c)
2
Uart
5
Ssc
2
Sd / Emmc
1
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
No
Adc Channels
6
Adc Resolution (bits)
10
Adc Speed (ksps)
220
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.08 to 1.32
Fpu
No
Mpu / Mmu
No / Yes
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- M40800 PDF datasheet
- SAM9260 PDF datasheet #2
- SAM9261 PDF datasheet #3
- SAM9R64 PDF datasheet #4
- SAM9R64 PDF datasheet #5
- Current page: 157 of 284
- Download datasheet (2Mb)
6.9
ARM DDI 0029G
Destination registers
Single register
Load multiple registers
The first cycle of the LDM instruction is used to calculate the address of the first word
to be transferred, while performing a prefetch from memory. The second cycle fetches
the first word, and performs the base modification. During the third cycle, the first word
is moved to the appropriate destination register while the second word is fetched from
memory, and the modified base is latched internally in case it is needed to restore
processor state after an abort. The third cycle is repeated for subsequent fetches until the
last data word has been accessed, then the final (internal) cycle moves the last word to
its destination register. The cycle timings are listed in Table 6-12.
The last cycle can be merged with the next instruction prefetch to form a single memory
N-cycle. If an abort occurs, the instruction continues to completion, but all register
modification after the abort is prevented. The final cycle is altered to restore the
modified base register (that could have been overwritten by the load activity before the
abort occurred).
When the PC is in the list of registers to be loaded the current instruction pipeline must
be invalidated.
The PC is always the last register to be loaded, so an abort at any point prevents the PC
from being overwritten.
LDM with PC as a destination register is not available in Thumb state. Use
Cycle
1
2
3
Note
Copyright © 1994-2001. All rights reserved.
to perform the same function.
Address
pc+2L
alu
pc+3L
pc+3L
Table 6-12 Load multiple registers instruction cycle operations
MAS[1:0]
i
2
i
nRW
0
0
0
Data
(pc+2L)
(alu)
-
nMREQ
0
1
0
Instruction Cycle Timings
SEQ
0
0
1
nOPC
0
1
1
6-15
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