SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 32
SAM9RL64
Manufacturer Part Number
SAM9RL64
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.SAM9260.pdf
(290 pages)
3.SAM9261.pdf
(248 pages)
4.SAM9R64.pdf
(903 pages)
5.SAM9R64.pdf
(52 pages)
Specifications of SAM9RL64
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
240 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
118
Ext Interrupts
118
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device
Spi
1
Twi (i2c)
2
Uart
5
Ssc
2
Sd / Emmc
1
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
No
Adc Channels
6
Adc Resolution (bits)
10
Adc Speed (ksps)
220
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.08 to 1.32
Fpu
No
Mpu / Mmu
No / Yes
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- M40800 PDF datasheet
- SAM9260 PDF datasheet #2
- SAM9261 PDF datasheet #3
- SAM9R64 PDF datasheet #4
- SAM9R64 PDF datasheet #5
- Current page: 32 of 284
- Download datasheet (2Mb)
Introduction
1.4
1.4.1
1-10
Instruction set summary
Format summary
Type
S
B
H
T
Addressing modes
This section provides a description of the instruction sets used on the ARM7TDMI
processor.
This section describes:
•
•
•
This section provides a summary of the ARM, and Thumb instruction sets:
•
•
A key to the instruction set tables is provided in Table 1-1.
The ARM7TDMI processor uses an implementation of the ARMv4T architecture. For
a complete description of both instruction sets, refer to the ARM Architecture Reference
Manual.
The ARM instruction set formats are shown in Figure 1-5 on page 1-11.
Format summary on page 1-10
ARM instruction summary on page 1-12
Thumb instruction summary on page 1-19.
ARM instruction summary on page 1-12
Thumb instruction summary on page 1-19.
Description
Condition field, see Table 1-6 on page 1-19.
Operand2, see Table 1-4 on page 1-18.
Control field, see Table 1-5 on page 1-18.
Sets condition codes, optional.
Byte operation, optional.
Halfword operation, optional.
Forces address translation. Cannot be used with pre-indexed addresses.
See Addressing modes on page 1-15.
A 32-bit constant, formed by right-rotating an 8-bit value by an even number of bits.
A comma-separated list of registers, enclosed in braces ( { and } ).
Copyright © 1994-2001. All rights reserved.
Table 1-1 Key to tables
ARM DDI 0029G
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