SAM9X25 Atmel Corporation, SAM9X25 Datasheet - Page 4
SAM9X25
Manufacturer Part Number
SAM9X25
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9261.pdf
(248 pages)
2.SAM9X25.pdf
(45 pages)
3.SAM9X25.pdf
(1145 pages)
4.SAM9X25.pdf
(45 pages)
5.SAM9X25.pdf
(1325 pages)
Specifications of SAM9X25
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
105
Ext Interrupts
105
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
3
Uart
7
Can
2
Lin
4
Ssc
1
Ethernet
2
Sd / Emmc
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
NO
External Bus Interface
1
Dram Memory
DDR/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9261 PDF datasheet
- SAM9X25 PDF datasheet #2
- SAM9X25 PDF datasheet #3
- SAM9X25 PDF datasheet #4
- SAM9X25 PDF datasheet #5
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- Download datasheet (2Mb)
Contents
iv
Chapter 4
Chapter 5
Chapter 6
Chapter 7
Chapter 8
Chapter 9
Chapter 10
Caches and Write Buffer
4.1
4.2
4.3
4.4
4.5
Tightly-Coupled Memory Interface
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
Bus Interface Unit
6.1
6.2
Noncachable Instruction Fetches
7.1
Coprocessor Interface
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
8.9
8.10
Instruction Memory Barrier
9.1
9.2
9.3
Embedded Trace Macrocell Support
10.1
Copyright © 2001-2003 ARM Limited. All rights reserved.
About the caches and write buffer .............................................................. 4-2
Write buffer ................................................................................................. 4-4
Enabling the caches ................................................................................... 4-5
TCM and cache access priorities ............................................................... 4-8
Cache MVA and Set/Way formats .............................................................. 4-9
About the tightly-coupled memory interface ............................................... 5-2
TCM interface signals ................................................................................. 5-4
TCM interface bus cycle types and timing .................................................. 5-8
TCM programmer’s model ........................................................................ 5-19
TCM interface examples ........................................................................... 5-20
TCM access penalties .............................................................................. 5-29
TCM write buffer ....................................................................................... 5-30
Using synchronous SRAM as TCM memory ............................................ 5-31
TCM clock gating ...................................................................................... 5-32
About the bus interface unit ........................................................................ 6-2
Supported AHB transfers ............................................................................ 6-3
About noncachable instruction fetches ....................................................... 7-2
About the ARM926EJ-S external coprocessor interface ............................ 8-2
LDC/STC .................................................................................................... 8-4
MCR/MRC .................................................................................................. 8-6
CDP ............................................................................................................ 8-8
Privileged instructions ................................................................................. 8-9
Busy-waiting and interrupts ...................................................................... 8-10
CPBURST ................................................................................................ 8-11
CPABORT ................................................................................................ 8-12
nCPINSTRVALID ..................................................................................... 8-13
Connecting multiple external coprocessors .............................................. 8-14
About the instruction memory barrier operation ......................................... 9-2
IMB operation ............................................................................................. 9-3
Example IMB sequences ............................................................................ 9-5
About Embedded Trace Macrocell support .............................................. 10-2
ARM DDI0198D
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