SAM9X25 Atmel Corporation, SAM9X25 Datasheet - Page 52
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SAM9X25
Manufacturer Part Number
SAM9X25
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9261.pdf
(248 pages)
2.SAM9X25.pdf
(45 pages)
3.SAM9X25.pdf
(1145 pages)
4.SAM9X25.pdf
(45 pages)
5.SAM9X25.pdf
(1325 pages)
Specifications of SAM9X25
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
105
Ext Interrupts
105
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
3
Uart
7
Can
2
Lin
4
Ssc
1
Ethernet
2
Sd / Emmc
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
NO
External Bus Interface
1
Dram Memory
DDR/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9261 PDF datasheet
- SAM9X25 PDF datasheet #2
- SAM9X25 PDF datasheet #3
- SAM9X25 PDF datasheet #4
- SAM9X25 PDF datasheet #5
- Current page: 52 of 248
- Download datasheet (2Mb)
Programmer’s Model
2.3.9
2-24
TLB Operations Register c8
31 32-A 31-A
Way
Test and clean operations
The test and clean DCache instruction provides an efficient way to clean the entire
DCache using a simple loop. The test and clean DCache instruction tests a number of
lines in the DCache to determine if any of them are dirty. If any dirty lines are found,
then one of those lines is cleaned. The test and clean DCache instruction also returns the
status of the entire DCache in bit 30.
The test and clean DCache instruction,
encoding that uses r15 as a destination operand. However, the PC is not changed by
using this instruction. This MRC instruction also sets the condition code flags.
If the cache contains any dirty lines, bit 30 is set to 0. If the cache contains no dirty lines,
bit 30 is set to 1. This means that you can use the following loop to clean the entire
DCache:
The test, clean, and invalidate DCache instruction is the same as test and clean DCache,
except that when the entire cache has been cleaned, it is invalidated. This means that
you can use the following loop to clean and invalidate the entire DCache:
This is a write-only register used to control the Translation Lookaside Buffer (TLB).
There is a single TLB used to hold entries for both data and instructions. The TLB is
divided into two parts:
•
•
Copyright © 2001-2003 ARM Limited. All rights reserved.
a set-associative part
a fully-associative part.
Note
SBZ
Figure 2-10 Register c7 Set/Way format
S+5 S+4
Set (= index)
5 4
, is a special
Word
ARM DDI0198D
2 1 0
SBZ
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