SAM9X35 Atmel Corporation, SAM9X35 Datasheet - Page 562
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SAM9X35
Manufacturer Part Number
SAM9X35
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9261.pdf
(248 pages)
2.SAM9X25.pdf
(45 pages)
3.SAM9X25.pdf
(1145 pages)
4.SAM9X25.pdf
(45 pages)
5.SAM9X25.pdf
(1325 pages)
Specifications of SAM9X35
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
105
Ext Interrupts
105
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
3
Uart
7
Can
2
Lin
4
Ssc
1
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
NO
External Bus Interface
1
Dram Memory
DDR/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9261 PDF datasheet
- SAM9X25 PDF datasheet #2
- SAM9X25 PDF datasheet #3
- SAM9X25 PDF datasheet #4
- SAM9X25 PDF datasheet #5
- Current page: 562 of 1145
- Download datasheet (26Mb)
33.7
Table 33-6.
Notes:
562
562
Offset
0x00
0x04
0x08 - 0x0C
0x10
0x14
0x18
0x1C
0x20 - 0xCC
0xE0
0xE4 - 0xE8
0xF0
0xF4
0xF8
0x100 + endpoint * 0x20 + 0x00
0x100 + endpoint * 0x20 + 0x04
0x100 + endpoint * 0x20 + 0x08
0x100 + endpoint * 0x20 + 0x0C
0x100 + endpoint * 0x20 + 0x10
0x100 + endpoint * 0x20 + 0x14
0x100 + endpoint * 0x20 + 0x18
0x100 + endpoint * 0x20 + 0x1C
0x120 - 0x1DC
0x300 + channel * 0x10 + 0x00
0x300 + channel * 0x10 + 0x04
0x300 + channel * 0x10 + 0x08
0x300 + channel * 0x10 + 0x0C
0x310 - 0x370
USB High Speed Device Port (UDPHS) User Interface
1. The reset value for UDPHS_EPTCTL0 is 0x0000_0001.
2. The addresses for the UDPHS Endpoint registers shown here are for UDPHS Endpoint0. The structure of this group of reg-
3. The DMA channel index refers to the corresponding EP number. When no DMA channel is assigned to one EP, the associ-
SAM9X25
SAM9X25
isters is repeated successively for each endpoint according to the consecution of endpoint registers located between 0x120
and 0x1DC.
ated registers are reserved. This is the case for EP0, so DMA Channel 0 registers are reserved.
Register Mapping
Register
UDPHS Control Register
UDPHS Frame Number Register
Reserved
UDPHS Interrupt Enable Register
UDPHS Interrupt Status Register
UDPHS Clear Interrupt Register
UDPHS Endpoints Reset Register
Reserved
UDPHS Test Register
Reserved
UDPHS Name1 Register
UDPHS Name2 Register
UDPHS Features Register
UDPHS Endpoint Configuration Register
UDPHS Endpoint Control Enable Register
UDPHS Endpoint Control Disable Register
UDPHS Endpoint Control Register
Reserved (for endpoint)
UDPHS Endpoint Set Status Register
UDPHS Endpoint Clear Status Register
UDPHS Endpoint Status Register
UDPHS Endpoint1 to 6
UDPHS DMA Next Descriptor Address Register
UDPHS DMA Channel Address Register
UDPHS DMA Channel Control Register
UDPHS DMA Channel Status Register
DMA Channel1 to 5
(3)
Registers
(2)
Registers
UDPHS_CTRL
UDPHS_FNUM
–
UDPHS_IEN
UDPHS_INTSTA
UDPHS_CLRINT
UDPHS_EPTRST
–
UDPHS_TST
–
UDPHS_IPNAME1
UDPHS_IPNAME2
UDPHS_IPFEATURES
UDPHS_EPTCFG
UDPHS_EPTCTLENB
UDPHS_EPTCTLDIS
UDPHS_EPTCTL
–
UDPHS_EPTSETSTA
UDPHS_EPTCLRSTA
UDPHS_EPTSTA
UDPHS_DMANXTDSC
UDPHS_DMAADDRESS
UDPHS_DMACONTROL
UDPHS_DMASTATUS
Name
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Read-only
Read-only
Write-only
Write-only
Read-only
Read-only
Read-only
Write-only
Write-only
Read-only
Write-only
Write-only
Read-only
Access
–
–
–
–
11054A–ATARM–27-Jul-11
11054A–ATARM–27-Jul-11
0x0000_0000
0x0000_0200
0x0000_0000
0x0000_0010
0x0000_0000
0x0000_0000
0x4855_5342
0x3244_4556
0x0000_0000
0x0000_0040
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
Reset
–
–
–
–
–
–
–
–
–
–
(1)
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