SAM9X35 Atmel Corporation, SAM9X35 Datasheet - Page 202
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SAM9X35
Manufacturer Part Number
SAM9X35
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9261.pdf
(248 pages)
2.SAM9X25.pdf
(45 pages)
3.SAM9X25.pdf
(1145 pages)
4.SAM9X25.pdf
(45 pages)
5.SAM9X25.pdf
(1325 pages)
Specifications of SAM9X35
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
105
Ext Interrupts
105
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
3
Uart
7
Can
2
Lin
4
Ssc
1
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
NO
External Bus Interface
1
Dram Memory
DDR/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9261 PDF datasheet
- SAM9X25 PDF datasheet #2
- SAM9X25 PDF datasheet #3
- SAM9X25 PDF datasheet #4
- SAM9X25 PDF datasheet #5
- Current page: 202 of 248
- Download datasheet (2Mb)
Signal Descriptions
A.8
A-14
TCM interface signals
Table A-7 describes the ARM926EJ-S TCM interface signals.
Signal
DRADDR[17:0]
DRCS
DRDMAADDR[17:0]
DRDMAEN
DRDMACS
DRIDLE
DRnRW
DRRD[31:0]
DRSEQ
Copyright © 2001-2003 ARM Limited. All rights reserved.
Direction
Output
Output
Input
Input
Input
Output
Output
Input
Output
Function
Data TCM address. This is the word address for the
access. Valid during request cycles.
Chip select. Indicates if an access will take place in
the following cycle. Not valid during wait cycles.
Direct memory access address for DTCM memory. If
DRDMAEN is set to 1, then the value of
DRDMAADDR is routed directly through to
DRADDR.
DMA access cycle.
If asserted, DRADDR is directly sourced from
DRDMAADDR, and DRCS is the result of logically
ORing DRDMACS with the chip select value for the
current TCM access.
Direct memory access chip-select for DTCM.
Data TCM interface idle:
0 = TCM access
1 = no access will take place in the current cycle or
TCM disabled.
Not valid for DMA accesses.
Data TCM read not write:
0 = read
1 = write.
Indicates if the access is a read or write. Valid during
request cycles.
Data TCM read data.
Valid during non-waited data cycles.
Request sequential.
Valid during request cycles, asserted during wait
cycles.
Indicates that the address in the current cycle is
sequential to the address used during the previous
request cycle.
Table A-7 TCM interface signals
ARM DDI0198D
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