SAM9X35 Atmel Corporation, SAM9X35 Datasheet - Page 245
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SAM9X35
Manufacturer Part Number
SAM9X35
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9261.pdf
(248 pages)
2.SAM9X25.pdf
(45 pages)
3.SAM9X25.pdf
(1145 pages)
4.SAM9X25.pdf
(45 pages)
5.SAM9X25.pdf
(1325 pages)
Specifications of SAM9X35
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
105
Ext Interrupts
105
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
3
Uart
7
Can
2
Lin
4
Ssc
1
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
NO
External Bus Interface
1
Dram Memory
DDR/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9261 PDF datasheet
- SAM9X25 PDF datasheet #2
- SAM9X25 PDF datasheet #3
- SAM9X25 PDF datasheet #4
- SAM9X25 PDF datasheet #5
- Current page: 245 of 248
- Download datasheet (2Mb)
Index
The items in this index are listed in alphabetical order. The references given are to page numbers.
A
A bit 2-14
Aborts, external 3-29
Access control, domain 3-24
Access permission bits 3-24
Access permissions 3-3
Access priorities, TCM and cache 4-8
Address alignment 6-6
Address translation 3-5
Addresses 2-4
AHB
Alignment fault 3-27
ARM926EJ-S
ARM DDI0198D
clocking 6-10
signals A-3
system considerations 6-6
transfers 6-3
enable/disable 2-14
block diagram 1-2
interfaces 1-3
programmer’s model 2-2
Copyright © 2001-2003 ARM Limited. All rights reserved.
Assoc field 2-10
B
Block diagram 1-2
Bus interface unit 6-2
Busy-waiting 8-10
Byte accesses 6-6
Byte lane indication 6-6
Byte writable memory 5-20
C
C and B bits
C bit 2-14
DCache 4-6
write-through (WT) 4-2
settings, ICache 4-5
Cache
CDP instructions 8-8
Clean and invalidate single data entry
Clean single data entry 2-21
access priorities 4-8
associativity encoding 2-10
debug control register B-12
enabling 4-5
features 4-2
lockdown regsiter 2-26
operations 2-21
operations register 2-21
RAMs 12-3
size encoding 2-10
type 2-9
type register 2-7, 2-8
type register example format 2-11
unlock procedure 2-29
way format 4-9
way, loading addresses 2-28
writeback (WB) 4-2
write-through (WT) 4-2
2-21
Index-1
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