SAM9XE128 Atmel Corporation, SAM9XE128 Datasheet - Page 120
SAM9XE128
Manufacturer Part Number
SAM9XE128
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9260.pdf
(290 pages)
2.SAM9261.pdf
(248 pages)
3.SAM9XE128.pdf
(860 pages)
4.SAM9XE128.pdf
(48 pages)
Specifications of SAM9XE128
Flash (kbytes)
128 Kbytes
Pin Count
217
Max. Operating Frequency
180 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
96
Ext Interrupts
96
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
2
Uart
6
Ssc
1
Ethernet
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
Yes
Adc Channels
4
Adc Resolution (bits)
10
Adc Speed (ksps)
312
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.65 to 1.95
Fpu
No
Mpu / Mmu
No / Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9260 PDF datasheet
- SAM9261 PDF datasheet #2
- SAM9XE128 PDF datasheet #3
- SAM9XE128 PDF datasheet #4
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Tightly-Coupled Memory Interface
5-12
In cycle T1, the ARM926EJ-S internal TCM controller is idle and DRIDLE is asserted.
DRDMAEN is asserted, and consequently the value of DRDMAADDR is propagated
onto DRADDR, and DRCS is asserted (DRDMACS = 1). DRSEQ is forced LOW.
In cycle T2, the ARM926EJ-S internal TCM controller is no longer idle, and DRIDLE
is deasserted. A nonsequential request is made to address B.
In cycle T3, a sequential request is made to address B+1 and DRSEQ is asserted
In cycle T4, the ARM926EJS internal TCM controller attempts to output values
corresponding to a sequential request to address B+2. DRDMAEN is asserted, and the
value of DRADDR and DRSEQ change accordingly. The ARM926EJ-S TCM
controller is stalled.
In cycle T5, DRDMAEN is deasserted and the ARM926EJ-S TCM controller re-issues
the request to address B+2. Because of the intervening DMA access, DRSEQ is
deasserted for the repeated request.
In cycle T6, a sequential request is made to address B+3 and DRSEQ is re-asserted.
DMA accesses can be made to the ITCM using the IRDMAEN, IRDMACS, and
IRDMAADDR signals but, unlike the DTCM, simultaneous access by the
ARM926EJ-S and DMA is not supported. This means that ITCM DMA must not take
place while executing code from the ITCM.
DRDMAADDR
DRDMAEN
DRDMACS
Copyright © 2001-2003 ARM Limited. All rights reserved.
DRADDR
DRIDLE
DRSEQ
DRCS
CLK
Figure 5-5 DMA access interaction with normal DTCM accesses
T1
A
A
T2
B
T3
B+1
B+2
T4
C
C
T5
B+2
ARM DDI0198D
T6
B+3
B+3
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