SAM9XE128 Atmel Corporation, SAM9XE128 Datasheet - Page 43
SAM9XE128
Manufacturer Part Number
SAM9XE128
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9260.pdf
(290 pages)
2.SAM9261.pdf
(248 pages)
3.SAM9XE128.pdf
(860 pages)
4.SAM9XE128.pdf
(48 pages)
Specifications of SAM9XE128
Flash (kbytes)
128 Kbytes
Pin Count
217
Max. Operating Frequency
180 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
96
Ext Interrupts
96
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
2
Uart
6
Ssc
1
Ethernet
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
Yes
Adc Channels
4
Adc Resolution (bits)
10
Adc Speed (ksps)
312
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.65 to 1.95
Fpu
No
Mpu / Mmu
No / Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9260 PDF datasheet
- SAM9261 PDF datasheet #2
- SAM9XE128 PDF datasheet #3
- SAM9XE128 PDF datasheet #4
- Current page: 43 of 248
- Download datasheet (2Mb)
ARM DDI0198D
Cache
ICache disabled
ICache enabled
ICache enabled
DCache disabled
DCache enabled
DCache enabled
MMU
Enabled or
disabled
Disabled
Enabled
Enabled or
disabled
Disabled
Enabled
•
Assuming that TCM regions are disabled, the caches behave as shown in Table 2-12.
If either the DCache or the ICache is disabled, then the contents of that cache are not
accessed. If the cache is subsequently re-enabled, the contents will not have changed.
To guarantee that memory coherency is maintained, the DCache must be cleaned of
dirty data before it is disabled.
Copyright © 2001-2003 ARM Limited. All rights reserved.
the RR bit.
Behavior
All instruction fetches are from external memory (AHB).
All instruction fetches are cachable, with no protection checks. All addresses are flat
mapped. That is VA = MVA = PA.
Instruction fetches are cachable or noncachable, and protection checks are performed.
All addresses are remapped from VA to PA, depending on the MMU page table entry.
That is, VA translated to MVA, MVA remapped to PA.
All data accesses are to external memory (AHB).
All data accesses are noncachable nonbufferable. All addresses are flat mapped. That
is VA = MVA = PA.
All data accesses are cachable or noncachable, and protection checks are performed.
All addresses are remapped from VA to PA, depending on the MMU page table entry.
That is, VA translated to MVA, MVA remapped to PA.
Table 2-12 Effects of Control Register on caches
Programmer’s Model
2-15
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