SAM9XE256 Atmel Corporation, SAM9XE256 Datasheet - Page 7

• Manufacturer Part Number: SAM9XE256
• Manufacturer: Atmel Corporation

Specifications of SAM9XE256

• Flash (kbytes): 256 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 180 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 6
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 312
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.65 to 1.95
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

List of Tables
ARM926EJ-S Technical Reference Manual
ARM DDI0198D
Table 2-1
Table 2-2
Table 2-3
Table 2-4
Table 2-5
Table 2-6
Table 2-7
Table 2-8
Table 2-9
Table 2-10
Table 2-11
Table 2-12
Table 2-13
Table 2-14
Table 2-15
Table 2-16
Table 2-17
Table 2-18
Table 2-19
Table 2-20
Table 2-21
Table 2-22
Change history .............................................................................................................. ii
CP15 register summary ............................................................................................ 2-3
Address types in ARM926EJ-S ................................................................................. 2-4
CP15 abbreviations ................................................................................................... 2-5
Reading from register c0 ........................................................................................... 2-7
Register 0, ID code ................................................................................................... 2-8
Ctype encoding ......................................................................................................... 2-9
Cache size encoding (M=0) .................................................................................... 2-10
Cache associativity encoding (M=0) ....................................................................... 2-10
Line length encoding ............................................................................................... 2-11
Example Cache Type Register format .................................................................... 2-11
Control bit functions register c1 ............................................................................... 2-13
Effects of Control Register on caches ..................................................................... 2-15
Effects of Control Register on TCM interface .......................................................... 2-16
Domain access control defines ............................................................................... 2-18
FSR bit field descriptions ........................................................................................ 2-19
FSR status field encoding ....................................................................................... 2-20
Function descriptions register c7 ............................................................................ 2-21
Cache operations c7 ............................................................................................... 2-22
Register c8 TLB operations ..................................................................................... 2-25
Cache Lockdown Register instructions ................................................................... 2-27
Cache Lockdown Register L bits ............................................................................. 2-28
TCM Region Register instructions .......................................................................... 2-29
Copyright © 2001-2003 ARM Limited. All rights reserved.
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