ATmega48PA Automotive Atmel Corporation, ATmega48PA Automotive Datasheet - Page 131
ATmega48PA Automotive
Manufacturer Part Number
ATmega48PA Automotive
Description
Manufacturer
Atmel Corporation
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16.10 Timer/Counter Timing Diagrams
9223B–AVR–09/11
The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).
The extreme values for the OCR1x Register represents special cases when generating a
PWM waveform output in the phase correct PWM mode. If the OCR1x is set equal to BOT-
TOM the output will be continuously low and if set equal to TOP the output will be set to high
for non-inverted PWM mode. For inverted PWM the output will have the opposite logic values.
If OCR1A is used to define the TOP value (WGM13:0 = 9) and COM1A1:0 = 1, the OC1A out-
put will toggle with a 50% duty cycle.
The Timer/Counter is a synchronous design and the timer clock (clk
clock enable signal in the following figures. The figures include information on when Interrupt
Flags are set, and when the OCR1x Register is updated with the OCR1x buffer value (only for
modes utilizing double buffering).
OCF1x.
Figure 16-10. Timer/Counter Timing Diagram, Setting of OCF1x, no Prescaling
Figure 16-11
Figure 16-11. Timer/Counter Timing Diagram, Setting of OCF1x, with Prescaler (f
Atmel ATmega48PA/88PA/168PA [Preliminary]
TCNTn
OCRnx
OCFnx
TCNTn
OCRnx
(clk
OCFnx
(clk
clk
clk
shows the same timing data, but with the prescaler enabled.
clk
clk
I/O
I/O
I/O
Tn
I/O
Tn
/1)
/8)
OCRnx - 1
OCRnx - 1
Figure 16-10
OCRnx
OCRnx
OCRnx Value
OCRnx Value
shows a timing diagram for the setting of
OCRnx + 1
OCRnx + 1
T1
) is therefore shown as a
OCRnx + 2
OCRnx + 2
clk_I/O
/8)
131
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