ADAU1701JSTZ Analog Devices Inc, ADAU1701JSTZ Datasheet
ADAU1701JSTZ
Specifications of ADAU1701JSTZ
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ADAU1701JSTZ Summary of contents
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FEATURES 28-/56-bit, 50 MIPS digital audio processor 2 ADCs: SNR of 100 dB, THD + N of − DACs: SNR of 104 dB, THD + N of −90 dB Complete standalone operation Self-boot from serial EEPROM Auxiliary ADC ...
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ADAU1701 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Revision History ............................................................................... 3 Functional Block Diagram .............................................................. 4 Specifications..................................................................................... 5 Analog Performance .................................................................... 5 Digital Input/Output.................................................................... 7 Power.............................................................................................. 7 Temperature Range ...................................................................... 7 PLL and Oscillator........................................................................ ...
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REVISION HISTORY 2/11—Rev Rev. A Moved Figure 1 ..................................................................................4 Changes to Specifications Section...................................................5 Changes to Table 8, Test Conditions/Comments Column ..........8 Reordered Figures in Digital Timing Diagrams Section .............9 Changes to Figure 2...........................................................................9 Changes to Figure 5 and ...
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ADAU1701 FUNCTIONAL BLOCK DIAGRAM 2-CHANNEL ANALOG INPUT FILTA/ ADC_RES 2 SELECT RESET SELFBOOT DIGITAL DIGITAL ANALOG ANALOG PLL PLL LOOP VDD GROUND VDD GROUND MODE 3. 1.8V ADAU1701 PLL REGULATOR STEREO ADC 28-/56-BIT, 50MIPS AUDIO ...
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SPECIFICATIONS AVDD = 3.3 V, DVDD = 1.8 V, PVDD = 3.3 V, IOVDD = 3.3 V, master clock input = 12.288 MHz, unless otherwise noted. ANALOG PERFORMANCE Specifications are guaranteed at 25°C (ambient). Table 1. Parameter ADC INPUTS Number ...
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ADAU1701 Specifications are guaranteed at 130°C (ambient). Table 2. Parameter ADC INPUTS Number of Channels Resolution Full-Scale Input Signal-to-Noise Ratio A-Weighted Dynamic Range A-Weighted Total Harmonic Distortion + Noise Interchannel Gain Mismatch Crosstalk DC Bias Gain Error DAC OUTPUTS Number ...
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DIGITAL INPUT/OUTPUT Table 3. Parameter Input Voltage, High Input Voltage, Low Input Leakage, High Input Leakage, Low Bidirectional Pin Pull-Up Current, Low MCLKI Input Leakage, High MCLKI Input Leakage, Low High Level Output Voltage Low Level Output Voltage Input Capacitance ...
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ADAU1701 REGULATOR 1 Table 7. Regulator Parameter DVDD Voltage 1 Regulator specifications are calculated using a Zetex Semiconductors FZT953 transistor in the circuit. DIGITAL TIMING SPECIFICATIONS 1 Table 8. Digital Timing Parameter t MIN MASTER CLOCK ...
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Parameter t MIN MULTIPURPOSE PINS AND RESET t GRT t GFT t GIL t 20 RLPW 1 All timing specifications are given for the default (I Digital Timing Diagrams t BIH INPUT_BCLK t BIL t LIS INPUT_LRCLK t SIS SDATA_INx ...
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ADAU1701 SDA SCL OUTPUT_BCLK t LOS OUTPUT_LRCLK t SODS t SODM SDATA_OUTx LEFT-JUSTIFIED MSB MODE SDATA_OUTx MODE SDATA_OUTx RIGHT-JUSTIFIED MODE 8-BIT CLOCKS (24-BIT DATA) 12-BIT CLOCKS (20-BIT DATA) 14-BIT CLOCKS (18-BIT DATA) 16-BIT CLOCKS (16-BIT DATA) t ...
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ABSOLUTE MAXIMUM RATINGS Table 9. Parameter Rating DVDD to GND 2.2 V AVDD to GND 4.0 V IOVDD to GND 4.0 V Digital Inputs DGND − 0.3 V, IOVDD + 0.3 ...
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ADAU1701 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Table 11. Pin Function Descriptions 1 Pin No. Mnemonic Type 1, 37, 42 AGND PWR 2 ADC0 A_IN 3 ADC_RES A_IN 4 ADC1 A_IN 5 RESET D_IN 6 SELFBOOT D_IN 7 ADDR0 D_IN 8 ...
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Pin No. Mnemonic Type 14 MP7 D_IO 15 MP6 D_IO 16 MP10 D_IO 17 VDRIVE A_OUT 18 IOVDD PWR 19 MP11 D_IO 20 ADDR1/CDATA/WB D_IN 21 CLATCH/WP D_IO 22 SDA/COUT D_IO 23 SCL/CCLK D_IO 26 MP9 D_IO/A_IO 27 MP8 ...
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ADAU1701 1 Pin No. Mnemonic Type 33 PGND PWR 34 PVDD PWR 35 PLL_LF A_OUT 36, 48 AVDD PWR 38, 39 PLL_MODE0, D_IN PLL_MODE1 40 CM A_OUT 41 FILTD A_OUT VOUT3 A_OUT 44 VOUT2 A_OUT 45 VOUT1 ...
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TYPICAL PERFORMANCE CHARACTERISTICS 0.20 0.15 0.10 0.05 0 –0.05 –0.10 –0.15 –0. FREQUENCY (kHz) Figure 8. ADC Pass-Band Filter Response 10 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 0 ...
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ADAU1701 SYSTEM BLOCK DIAGRAM 18kΩ AUDIO ADC INPUT SIGNALS 18kΩ 18kΩ + 10µF MULTIPURPOSE PIN INTERFACES ADCs DACs 3.3V 475Ω 3.3nF 56nF PLL SETTINGS 3MHz TO 25MHz 22pF 100Ω 22pF 3.3V 100nF 100nF 100nF 100nF 10µF 10µ IOVDD ...
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THEORY OF OPERATION The core of the ADAU1701 is a 28-bit DSP (56-bit with double- precision processing) optimized for audio processing. The program and parameter RAMs can be loaded with a custom audio processing signal flow built by using SigmaStudio ...
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ADAU1701 INITIALIZATION This section details the procedure for properly setting up the ADAU1701. The following five-step sequence provides an overview of how to initialize the IC: 1. Apply power to ADAU1701. 2. Wait for PLL to lock. 3. Load SigmaDSP ...
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The ADC power-down mode powers down both ADCs, and each DAC can be powered down individually. The current savings is about 15 mA when the ADCs are powered down and about 4 mA for each DAC that ...
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ADAU1701 VOLTAGE REGULATOR The digital voltage of the ADAU1701 must be set to 1.8 V. The chip includes an on-board voltage regulator that allows the device to be used in systems without an available 1.8 V supply but with an ...
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AUDIO ADCs The ADAU1701 has two Σ-Δ ADCs. The signal-to-noise ratio (SNR) of the ADCs is 100 dB, and the THD + N is −83 dB. The stereo audio ADCs are current input; therefore, a voltage- to-current resistor is required ...
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ADAU1701 AUDIO DACs The ADAU1701 includes four Σ-Δ DACs. The SNR of the DAC is 104 dB, and the THD + N is −90 dB. A full-scale output on the DACs is 0.9 V rms (2.5 V p-p). The DACs ...
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CONTROL PORTS The ADAU1701 can operate in one of three control modes: • control • SPI control • Self-boot (no external controller) The ADAU1701 has both a 4-wire SPI control port and a 2-wire ...
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ADAU1701 PORT The ADAU1701 supports a 2-wire serial (I microprocessor bus driving multiple peripherals. Two pins, serial data (SDA) and serial clock (SCL), carry information between the ADAU1701 and the system mode, ...
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SCL SDA START BY MASTER FRAME 1 CHIP ADDRESS BYTE SCL (CONTINUED) SDA (CONTINUED) FRAME 3 SUBADDRESS BYTE 2 SCL SDA START BY MASTER FRAME 1 CHIP ADDRESS BYTE SCL (CONTINUED) ...
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ADAU1701 Read and Write Operations Figure 22 shows the timing of a single-word write operation. Every ninth clock, the ADAU1701 issues an acknowledge by pulling SDA low. Figure 23 shows the timing of a burst mode write ...
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SPI PORT 2 By default, the ADAU1701 mode, but it can be put into SPI control mode by pulling CLATCH/WP low three times. The SPI port uses a 4-wire interface, consisting of CLATCH, CCLK, CDATA, and ...
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ADAU1701 SELF-BOOT On power-up, the ADAU1701 can load a program and a set of parameters that have been saved in an external EEPROM. Combined with the auxiliary ADC and the multipurpose pins, this eliminates the need for a microcontroller in ...
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The writeback function writes data from the ADAU1701 interface registers to the second page of the self-boot EEPROM, Address 32 to Address 63. Starting at EEPROM Address 26 (so that the interface register data begins at Address 32), the EEPROM ...
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ADAU1701 SIGNAL PROCESSING The ADAU1701 is designed to provide all audio signal processing functions commonly used in stereo or multichannel playback systems. The signal processing flow is designed using the SigmaStudio software, which allows graphical entry and real- time control ...
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RAMS AND REGISTERS Table 21. RAM Map and Read/Write Modes Memory Size Parameter RAM 1024 × 32 Program RAM 1024 × Internal registers should be cleared first to avoid clicks/pops. ADDRESS MAPS Table 21 shows the RAM map ...
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ADAU1701 Table 22. Parameter RAM Read/Write Format (Single Address) Byte 0 Byte 1 chip_adr[6:0], W/R 000000, param_adr[9:8] Table 23. Parameter RAM Block Read/Write Format (Burst Mode) Byte 0 Byte 1 chip_adr[6:0], W/R 000000, param_adr[9:8] Table 24. Program RAM Read/Write Format ...
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CONTROL REGISTER MAP 1 Table 32. Register Map MSB Register No. Address of D31 D30 D29 D28 D27 D26 D25 D24 Hex Dec Bytes Name D15 D14 D13 D12 D11 D10 D9 0x0800 2048 4 Interface 0[31:16] 0 Interface 0[15:0] ...
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ADAU1701 MSB Register No. Address of D31 D30 D29 D28 D27 D26 D25 D24 Hex Dec Bytes Name D15 D14 D13 D12 D11 D10 D9 0x0820 2080 3 MP Pin Config. 0[23:16] MP Pin Config. 0[15:0] MP33 MP32 MP31 MP30 ...
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CONTROL REGISTER DETAILS 2048 TO 2055 (0x0800 TO 0x0807)—INTERFACE REGISTERS The interface registers are used in self-boot mode to save parameters that need to be written to the external EEPROM. The ADAU1701 then recalls these parameters from the EEPROM after ...
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ADAU1701 2056 (0x0808)—GPIO PIN SETTING REGISTER This register allows the user to set the GPIO pins through the control port. High or low settings can be directly written to or Table 35. GPIO Pin Setting Register Bit Map D15 D14 ...
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TO 2060 (0x0809 TO 0x080C)—AUXILIARY ADC DATA REGISTERS These registers hold the data generated by the 4-channel auxiliary ADC. The ADCs have eight bits of precision and can be extended to 12 bits if filtering is selected via Bits ...
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ADAU1701 2064 TO 2068 (0x0810 TO 0x0814)—SAFELOAD DATA REGISTERS Many applications require real-time microcontroller control of signal processing parameters, such as filter coefficients, mixer gains, multichannel virtualizing parameters, or dynamics processing curves. When controlling a biquad filter, for example, all ...
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TO 2075 (0x081A TO 0x081B)—DATA CAPTURE REGISTERS The ADAU1701 data capture feature allows the data at any node in the signal processing flow to be sent to one of two readable registers. This feature is useful for monitoring and ...
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ADAU1701 2076 (0x081C)—DSP CORE CONTROL REGISTER Table 46. DSP Core Control Register Bit Map D15 D14 D13 D12 D11 RSVD RSVD GD1 GD0 RSVD Table 47. DSP Core Control Register Bit Name Description GD[1:0] GPIO Debounce Control. Sets debounce time ...
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OUTPUT CONTROL REGISTER Table 48. Serial Output Control Register Bit Map D15 D14 D13 D12 D11 D10 0 0 OLRP OBP M/S OBF1 Table 49. Bit Name Description OLRP OUTPUT_LRCLK Polarity. When this bit is set to 0, ...
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ADAU1701 2079 (0x081F)—SERIAL INPUT CONTROL REGISTER Table 50. Serial Input Control Register Bit Map Table 51. Bit Name Description ILP INPUT_LRCLK Polarity. When this bit is set to 0, the left-channel data on the ...
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TO 2081 (0x0820 TO 0x0821)— MULTIPURPOSE PIN CONFIGURATION REGISTERS Each multipurpose pin can be set to different functions from these registers (2080 to 2081). The two 3-byte registers are broken up into 12 4-bit (nibble) sections that each control ...
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ADAU1701 2082 (0x0822)—AUXILIARY ADC AND POWER CONTROL Table 55. Auxiliary ADC and Power Control Bit Map D15 D14 D13 D12 D11 RSVD RSVD RSVD RSVD RSVD Table 56. Bit Name Description FIL[1:0] Auxiliary ADC filtering FIL[1: ...
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SETUP To properly initialize the DACs, Bits DS[1:0] in this register should be set to 01. Table 61. DAC Setup Bit Map D15 D14 D13 D12 D11 RSVD RSVD RSVD RSVD RSVD Table 62. Bit Name Description DS[1:0] ...
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ADAU1701 MULTIPURPOSE PINS The ADAU1701 has 12 multipurpose (MP) pins that can be individually programmed to be used as serial data inputs, serial data outputs, digital control inputs/outputs to and from the SigmaDSP core, or inputs to the 4-channel auxiliary ...
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The serial data clocks need to be synchronous with the ADAU1701 master clock input. The input control register allows control of clock polarity and data input modes. The valid data formats are I right-justified (24-/20-/18-/16-bit), and 8-channel TDM. In all ...
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ADAU1701 LEFT CHANNEL LRCLK BCLK SDATA MSB LRCLK LEFT CHANNEL BCLK MSB SDATA LEFT CHANNEL LRCLK BCLK SDATA MSB LRCLK BCLK DATA LRCLK BCLK MSB TDM SDATA CH 0 SLOT 0 SLOT 1 32 BCLKs LSB 1 Figure ...
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LAYOUT RECOMMENDATIONS PARTS PLACEMENT The ADC input voltage-to-current resistors and the ADC current set resistor should be placed as close as possible to the 2, 3, and 4 input pins. All 100 nF bypass capacitors, which are recommended for every ...
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ADAU1701 TYPICAL APPLICATION SCHEMATICS SELF-BOOT MODE U1 ADAU1701 Figure 37. Self-Boot Mode Schematic Rev Page ...
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I C CONTROL U1 ADAU1701 2 Figure 38 Control Schematic Rev Page ADAU1701 ...
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ADAU1701 SPI CONTROL U1 ADAU1701 Figure 39. SPI Control Schematic Rev Page ...
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... OUTLINE DIMENSIONS 1.45 1.40 1.35 0.15 SEATING 0.05 PLANE VIEW A ROTATED 90° CCW ORDERING GUIDE 1 Model Temperature Range ADAU1701JSTZ 0°C to +70°C ADAU1701JSTZ-RL 0°C to +70°C EVAL-ADAU1401EBZ EVAL-ADAU1701MINIZ RoHS Compliant Part. 9.20 9.00 SQ 0.75 1.60 8.80 0.60 MAX 0. PIN 1 TOP VIEW ...
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ADAU1701 NOTES Rev Page ...
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NOTES Rev Page ADAU1701 ...
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ADAU1701 NOTES ©2007–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06412-0-2/11(A) Rev Page ...