CS181012-CQZ Cirrus Logic Inc, CS181012-CQZ Datasheet - Page 20
![IC COBRANET CS181012 144LQFP](/photos/7/3/70376/mfg_cs18101_series_sml.jpg)
CS181012-CQZ
Manufacturer Part Number
CS181012-CQZ
Description
IC COBRANET CS181012 144LQFP
Manufacturer
Cirrus Logic Inc
Series
CobraNet®r
Type
Audio Processorr
Specifications of CS181012-CQZ
Package / Case
144-LQFP
Applications
Data Transport
Mounting Type
Surface Mount
Mounting Style
SMD/SMT
Number Of Converters
8
Core Size
32 Bit
Digital Ic Case Style
LQFP
No. Of Pins
144
Supply Voltage Range
1.71V To 1.89V
Operating Temperature Range
0°C To +70°C
Filter Terminals
SMD
Supply Voltage Min
3.13V
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1021 - MODULE COBRANET 4961 CM2 FB598-1020 - MODULE COBRANET 1810 CM2 MT
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
598-1025
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CS181012-CQZ
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
Company:
Part Number:
CS181012-CQZR
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
CobraNet Hardware User’s Manual
Digital Audio Interface
6.1
20
Digital Audio Interface Timing
Although data is always transmitted and received with a 32-bit resolution by the
synchronous serial ports, the resolution of the data transferred to/from the Ethernet may
be less. Incoming audio data is truncated to the selected resolution. Unused least
significant bits on outgoing data is zero filled.
An DAO1_SCLK edge follows an MCLK_OUT edge by 0.0 to 5.0ns. An FS1 edge follows
a MCLK_OUT edge by 0.0 to 10.0ns.
Setup times for DAI1_DATAx and FS1 are 5.0 ns with a hold time of 0.0 ns with respect to
the DAI1_SCLK edge. Clock to output times for DAO1_DATAx is 0.0 to 12.0 ns from the
edge of DAO1_SCLK.
DAO1_DATAx
DAI1_DATAx
DAO1_SCLK
DAO1_SCLK
MCLK_OUT
Figure 6. Timing Relationship between FS512_OUT, DAO1_SCLK and FS1
Note: The DAO1_SCLK and FS1 might be synchronized with the either the falling edge or
FS1
the rising edge of MCLK_OUT. Which edge is impossible to predict since it depends
on power up timing.
Figure 7. Serial Port Data Timing Overview
©
Copyright 2005 Cirrus Logic, Inc.
0 – 12ns
≥5ns
0 – 10ns
0 – 5ns
≥0ns
DS651UM23
Version 2.3