CS181012-CQZ Cirrus Logic Inc, CS181012-CQZ Datasheet - Page 26
![IC COBRANET CS181012 144LQFP](/photos/7/3/70376/mfg_cs18101_series_sml.jpg)
CS181012-CQZ
Manufacturer Part Number
CS181012-CQZ
Description
IC COBRANET CS181012 144LQFP
Manufacturer
Cirrus Logic Inc
Series
CobraNet®r
Type
Audio Processorr
Specifications of CS181012-CQZ
Package / Case
144-LQFP
Applications
Data Transport
Mounting Type
Surface Mount
Mounting Style
SMD/SMT
Number Of Converters
8
Core Size
32 Bit
Digital Ic Case Style
LQFP
No. Of Pins
144
Supply Voltage Range
1.71V To 1.89V
Operating Temperature Range
0°C To +70°C
Filter Terminals
SMD
Supply Voltage Min
3.13V
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1021 - MODULE COBRANET 4961 CM2 FB598-1020 - MODULE COBRANET 1810 CM2 MT
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
598-1025
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CS181012-CQZ
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
Company:
Part Number:
CS181012-CQZR
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
CobraNet Hardware User’s Manual
Host Management Interface (HMI)
7.3 Host Port Timing - Intel
(C
NOTES:1. The system designer should be aware that the actual maximum speed of the communication port may
26
Address setup before HCS and HRD low or HCS and HWR
low
Address hold time after HCS and HRD low or HCS and HWR
high
Delay between HRD then HCS low or HCS then HRD low
Data valid after HCS and HRD low
HCS and HRD low for read
Data hold time after HCS or HRD high
Data high-Z after HCS or HRD high
HCS or HRD high to HCS and HRD low for next read
HCS or HRD high to HCS and HWR low for next write
HRD rising to HREQ rising
Delay between HWR then HCS low or HCS then HWR low
Data setup before HCS or HWR high
HCS and HWR low for write
Data hold after HCS or HWR high
HCS or HWR high to HCS and HRD low for next read
HCS or HWR high to HCS and HWR low for next write
HWR rising to HREQ falling
L
= 20 pF)
be limited by the firmware application. Hardware handshaking on the HREQ pin/bit should be observed
to prevent overflowing the input data buffer.
Parameter
Write
Read
®
Mode
©
Copyright 2005 Cirrus Logic, Inc.
Symbol
t
t
irdirqhl
iwrbsyl
t
t
t
t
t
t
t
t
t
t
irdtw
iwpw
iwtrd
t
t
t
t
icdw
idhw
irpw
t
idsu
idhr
icdr
idis
iwd
iah
idd
ias
ird
Min
24
30
30
24
30
30
5
5
0
8
0
8
8
-
-
-
-
Max
18
18
12
12
-
-
-
-
-
-
-
-
-
-
-
-
-
DS651UM23
Version 2.3
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns