CS3308-CQZ Cirrus Logic Inc, CS3308-CQZ Datasheet - Page 40
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CS3308-CQZ
Manufacturer Part Number
CS3308-CQZ
Description
IC ANLG VOL CTRL 8CH DGTL 48LQFP
Manufacturer
Cirrus Logic Inc
Type
Controllerr
Datasheet
1.CS3308-CQZ.pdf
(44 pages)
Specifications of CS3308-CQZ
Package / Case
48-LQFP
Applications
High End Audio
Mounting Type
Surface Mount
Product
General Purpose Audio Amplifiers
Output Power
362 mW
Available Set Gain
22 dB
Thd Plus Noise
- 112 dB
Operating Supply Voltage
3.5 V / 5.25 V
Supply Current
36 mA
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Audio Load Resistance
2 KOhms
Input Offset Voltage
0.75 V
Input Signal Type
Single
Minimum Operating Temperature
- 10 C
Output Signal Type
Analog
Supply Voltage (max)
5.25 V
Supply Voltage (min)
3.1 V
Output Type
8-Channel Audio
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1778 - EVALUATION BOARD FOR CS5376598-1496 - BOARD EVAL FOR CS3308 VOL CTRL
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
598-1598
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CS3308-CQZR
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
40
7.18
7.18.1 Group 2 Chip Address (Bits 7:1)
7.18.2 Enable Group 2 Address (Bit 0)
7.19
7.19.1 Group 1 Chip Address (Bits 7:1)
7.19.2 Enable Group 1 Address (Bit 0)
G2_Addr6
G1_Addr6
7
7
Group 2 Chip Address 19h
Group 1 Chip Address 1Ah
SPI Mode Default = 1000000b
I²C Mode Default = See
Function:
Default = 0
Function:
SPI Mode Default = 1000000b
I²C Mode Default = See
Function:
Default = 0
Function:
These bits set the Group 2 chip address, and may be modified at any time. See
trol Configuration” on page 23
This bit controls the device’s recognition of the Group 2 address. When set, the device will respond
to serial communication when addressed with the Group 2 address. When cleared, the device will ig-
nore all serial communication when addressed with the Group 2 address.
These bits set the Group 1 chip address, and may be modified at any time. See
trol Configuration” on page 23
This bit controls the device’s recognition of the Group 1 address. When set, the device will respond
to serial communication when addressed with the Group 1 address. When cleared, the device will ig-
nore all serial communication when addressed with the Group 1 address.
G2_Addr5
G1_Addr5
6
6
G2_Addr4
G1_Addr4
Table 4 on page
Table 4 on page
5
5
and
and
G2_Addr3
G1_Addr3
“I²C/SPI Serial Control Formats” on page 27
“I²C/SPI Serial Control Formats” on page 27
4
4
27.
27.
G2_Addr2
G1_Addr2
3
3
G2_Addr1
G1_Addr1
2
2
G2_Addr0
G1_Addr0
1
1
for more information.
for more information.
“System Serial Con-
“System Serial Con-
EnG2Addr
EnG1Addr
CS3308
DS702F1
0
0