CS8420-DSZ Cirrus Logic Inc, CS8420-DSZ Datasheet - Page 49

• Manufacturer Part Number: CS8420-DSZ
• Description: IC CONV S/R DGTL AUDIO 28-SOIC
• Manufacturer: Cirrus Logic Inc
• Type: Sample Rate Converterr

Specifications of CS8420-DSZ

• Applications: Digital Audio
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC
• Audio Control Type: Sample Rate Converter
• Control Interface: 3 Wire, Serial
• Supply Voltage Range: 4.75V To 5.25V
• Operating Temperature Range: -40°C To +85°C
• Audio Ic Case Style: SOIC
• No. Of Pins: 28
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 598-1729

DS245F4
11.3
11.4
SRC Invalid State
Occasionally the CS8420 SRC will enter an invalid state. This can happen after the RUN bit has been set
when an AES3 stream is first plugged into the part or when a source device interrupts the SRC input stream.
When this happens, two symptoms may be noticeable: notches occurring in the frequency response and
spurious tones being generated in response to some input frequencies.
To avoid this problem in Software mode, use the microcontroller to monitor the UNLOCK bit in control reg-
ister 10h. When the part achieves lock, clear the RUN bit in register 4 and then set it again. This will reset
all internal state machines. Alternately, the user may use the following sequence:
1. Power on CS8420.
2. Write the following register sequence:
3. Wait for PLL to lock.
4. Wait 250ms for SRC to lock.
5. Write the following register sequence:
6. If PLL goes out of lock, start at step 2 and repeat.
When synchronizing multiple CS8420s, wait for all PLLs to lock before continuing to the next step. These
actions clear the invalid state if it has occurred.
In Hardware mode, monitor the RERR pin for receiver lock status. When the part achieves lock, set the RST
pin low for at least 200 μs and then set it high again. This action clears the invalid state if it has occurred.
When polling the RERR pin again, the user must account for the fact that the RERR pin will be high during
reset and remain high until the PLL has reachieved lock.
In either Software or Hardware mode, when clearing the invalid state, it is advisable to mute any devices
connected to the output of the CS8420.
C/U Buffer Data Corruption
Occasionally the C/U buffer data may be corrupted. This can happen after the RUN bit has been set and
data has been written to the C/U buffer (20h-37h). If no further data is written to the C buffer after the initial
write and the receiver input is interrupted multiple times, the contents of the buffer may be reset to all zeros.
The buffer will not be corrupted if the buffer data is being updated, only when the data is static and the re-
ceiver input has been interrupted multiple times.
To avoid this problem in Software mode when the C/U buffer contents should remain static, use the micro-
controller to monitor the UNLOCK bit in control register 10h or the RERR pin. If the part indicates the PLL
has lost lock, rewrite the C/U buffer data. Repeat this action every time the PLL goes out of lock.
In Hardware mode, this limitation does not exist as the serial C/U data is being fed directly to the transmitter.
Register
Register
04h
03h
04h
03h
04h
Value
Value
09h
95h
49h
81h
41h
CS8420
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