CS8420-DSZ Cirrus Logic Inc, CS8420-DSZ Datasheet - Page 67

• Manufacturer Part Number: CS8420-DSZ
• Description: IC CONV S/R DGTL AUDIO 28-SOIC
• Manufacturer: Cirrus Logic Inc
• Type: Sample Rate Converterr

Specifications of CS8420-DSZ

• Applications: Digital Audio
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC
• Audio Control Type: Sample Rate Converter
• Control Interface: 3 Wire, Serial
• Supply Voltage Range: 4.75V To 5.25V
• Operating Temperature Range: -40°C To +85°C
• Audio Ic Case Style: SOIC
• No. Of Pins: 28
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 598-1729

DS245F4
13.5
Hardware Mode 4 Description
(Transceive Data Flow, No SRC)
Hardware mode 4 data flow is shown in
the serial audio output port. Different audio data synchronous to RMCK may be input into the serial audio
input port, and output via the AES3 transmitter.
The channel status data, user data, and validity bit information are handled in two alternative modes: 4A
and 4B, determined by a start-up resistor on the COPY pin. In mode 4A, the received PRO, COPY, ORIG,
EMPH, and AUDIO channel status bits are output on pins. The transmitted channel status bits are copied
from the received channel status data, and the transmitted U and V bits are 0.
In mode 4B, only the COPY and ORIG pins are output, and reflect the received channel status data. The
transmitted channel status bits, user data, and validity bits are input serially via the PRO/C, EMPH/U, and
AUDIO/V pins.
The APMS pin allows the serial audio input port to be set to master or slave.
If a validity, parity, bi-phase, or lock receiver error occurs, the current audio sample is passed unmodified
to the serial audio output port.
Start-up options are shown in
whether TCBL is an input or an output, the audio serial ports formats, and the source of the transmitted C,
U, and V data.
The following pages contain the detailed pin descriptions for Hardware mode 4.
RXP
RXN
Figure 20
RMCK
Power supply pins (VD+, VA+, DGND, AGND) & the reset pin (RST) and the PLL filter pin (FILT)
are omitted from this diagram. Please refer to the Typical Connection Diagram for hook-up details.
Figure 27. Hardware Mode 4 - Transceive Data Flow, Without SRC
DFC0
AES3 Rx
&
Decoder
RERR
VD+
shows the timing requirements.
DFC1
Table
VD+
13, and allow choice of the serial audio output port as a master or slave,
H/S
Figure
PRO/C
SDOUT
27. Audio data is input via the AES3 receiver, and routed to
OSCLK
Serial
Audio
Output
COPY ORIG EMPH/U AUDIO/V TCBL
OLRCK
C & U bit Data Buffer
ILRCK
ISCLK
Serial
Audio
Input
SDIN
AES3
Encoder
& Tx
APMS
TXP
TXN
CS8420
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