IRS20954STRPBF International Rectifier, IRS20954STRPBF Datasheet
IRS20954STRPBF
Specifications of IRS20954STRPBF
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IRS20954STRPBF Summary of contents
Page 1
Not recommended for new designs. Features • Floating PWM input enables easy half bridge implementation • Integrated programmable bi-directional over-current protection with self-reset function • Programmable compensated preset deadtime for improved THD performances • High noise immunity • ±100 V ...
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Not recommended for new designs. Absolute Maximum Ratings Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM; all currents are defined positive into any lead. The ...
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Not recommended for new designs. Recommended Operating Conditions For proper operation, the device should be used within the recommended conditions below. The V ratings are tested with supplies biased at I Symbol V High-side floating supply absolute voltage B V ...
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Not recommended for new designs. Electrical Characteristics (cont.) Definition Symbol Floating PWM Input V Logic high input threshold voltage IH V Logic low input threshold voltage IL I Logic “1” input bias current IN+ I Logic “0” input bias current ...
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Not recommended for new designs. Electrical Characteristics (cont.) Definition Symbol V DT mode select threshold 2 DT1 V DT mode select threshold 3 DT2 V DT mode select threshold 4 DT3 Lead Definitions Symbol Pin # VDD Floating input positive ...
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Not recommended for new designs. Block Diagram VDD IN 10.4V VSS CHARGE/ DISCHARGE CSD LEVEL PROTECTION CONTROL LEVEL www.irf.com Please use IRS20957SPBF. FLOATING INPUT UV DETECT INPUT LOGIC HV LEVEL HV SHIFT FLOATING HIGH SIDE LEVEL SHIFT 5V REG DEAD-TIME ...
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Not recommended for new designs. Figure 1: Switching Time Waveform Definitions CSD HO/LO Figure 2: CSD to Shutdown Waveform Definitions www.irf.com Please use IRS20957SPBF. Vth1 t SD IRS20954SPBF 90% 7 ...
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Not recommended for new designs. CSD HO/LO Figure 3: CSH to Shutdown Waveform Definitions VS LO Figure 4: V www.irf.com Please use IRS20957SPBF. Vth1 THCSL t OCL > Shutdown Waveform Definitions s TH,SCL IRS20954SPBF 90% ...
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Functional Description Floating PWM Input The IRS20954 has a floating input interface which enables easy half bridge implementation. Three pins, V and IN, are referenced result, the PWM input signal can be directly fed into ...
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Not recommended for new designs. Protection Control The internal protection control block manages operational mode between shutdown and normal, with a help from CSD pin. Shutdown mode forces LO and HO to output the COM and V ...
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Not recommended for new designs. Self Reset Protection By simply putting a capacitor between the CSD and V Designing Ct Timing capacitor Ct programs the protection resume interval timing t ⋅ ⋅ ...
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Not recommended for new designs. Latched Protection Connecting CSD to V through a 10 kΩ or less resistor configures the IRS20954 as a latched over-current protection. DD The over-current protection stays in shutdown mode after over-current condition detected. To reset ...
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Not recommended for new designs. HIGH SIDE CS HV FLOATING HIGH SIDE LEVEL SHIFT 5V REG DETECT DEAD TIME SD Low-side Over-Current Sensing For the negative load current, low-side over-current sensing monitors over load condition and shutdown the switching operation ...
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Not recommended for new designs. Since the sensed voltage compared with the voltages fed to the OCSET pin, the required voltage of OCSET with S respect to COM for a trip level I TRIP ...
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Not recommended for new designs. CSH Comparator + OC - 1.2V IRS20954 Figure 14: Programming High-side Over-Current Threshold OCP Design Example High-side Over-current Setting Fig. 14 demonstrates the typical peripheral circuit of high-side current sensing. For example, the over-current protection ...
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Not recommended for new designs. Low-side Over-current Setting Designing with the same MOSFET as in high-side with R trip level is given by 100 m OCSET TRIP+ DS(ON) Choose R4+R5=10 kΩ ...
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Not recommended for new designs. A longer dead time period is required for a MOSFET with a larger gate charge value because of the longer t effective deadtime setting is always beneficial to achieve better linearity in the Class D ...
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Not recommended for new designs. Table 1 shows suggested values of resistance for setting the deadtime. Resistors with tolerance can be used if these listed values are followed. Table 1: Suggested Resistor Values for Deadtime Settings Power ...
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Not recommended for new designs. PWM Charging V Prior to start BS The high-side bootstrap power supply can be charged up through a resistor from the positive supply bus to V internal 20.8 V zener diode clamp between V for ...
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Not recommended for new designs. time the voltage at CSD pin reached the release threshold, V for the low-side and high-side are disabled until UVLO of V Power-down Sequence As soon reaches the UVLO negative going ...
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Not recommended for new designs. Junction Temperature Estimation The power dissipation in the IRS20954 consists of following dominant items dissipation in floating input logic and protection MID - P : dissipation in low-side LOW - P : ...
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Not recommended for new designs HIGH LDD HO ⎛ ⎜ = ⋅ + ⋅ ⋅ ⋅ ⎜ + QBS ⎝ O Where P ...
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Not recommended for new designs. Case Outline NOTES: 1. DIMENSIONING & TOLERANCING PER ANSI Y14.5W-1982 2. CONTROLLING DIMENSION. MILLIMETER 3. DIMENSIONS ARE SHOWN IN MILLIMETER [INCHES] 4. OUTLINE CONFORMS TO JEDEC OUTLINE MS-012AC 5. DIMENSION IS THE LENGTH OF LEAD ...
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Not recommended for new designs. F NOTE : CONTROLLING DIM ENSION CARRIER TAPE DIMENSION FOR 16SOICN Code REEL DIMENSIONS FOR 16SOICN Code ...
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... WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105 www.irf.com Please use IRS20957SPBF. ORDER INFORMATION 16-Lead SOIC IRS20954SPbF 16-Lead SOIC Tape & Reel IRS20954STRPbF This product has been designed and qualified for the industrial level. Qualification standards can be found at Data and specifications subject to change without notice 07/05/2007 IRS20954SPBF SO-16 package is MSL3 qualified. IR’ ...