LT1394CS8#TR Linear Technology, LT1394CS8#TR Datasheet - Page 13

• Manufacturer Part Number: LT1394CS8#TR
• Description: IC COMPARATOR 7NS LOW PWR 8SOIC
• Manufacturer: Linear Technology
• Series: UltraFast™r
• Type: General Purposer

Specifications of LT1394CS8#TR

• Number Of Elements: 1
• Output Type: CMOS, Complementary, TTL
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (0.154", 3.90mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

INPUT
APPLICATIONS
Fast, High Impedance, Variable Threshold Trigger
A frequent requirement in instrumentation is a fast trigger
with a variable threshold. Often, a high impedance input is
also required. Figure 15 meets these requirements. Com-
parator C1 is the basic trigger, with threshold voltage set at
its negative input. Source follower Q1 provides high
impedance with about 2pF input capacitance and 50pA bias
current. Normally, Q1’s source bias point would be uncer-
tain and drifty, but stabilization techniques eliminate this
concern. A1 measures filtered versions of Q1’s gate and
source voltages. A1’s output biases Q2, forcing Q1’s
channel current to whatever value is required to equalize
A1’s inputs, and hence Q1’s gate and source voltages. A1’s
input filtering and roll-off are far slower than input frequen-
cies of interest; its action does not interfere with the
circuit’s main signal path. The 330pF capacitor prevents
fast edges coupled through Q2’s collector base junction
from influencing A1’s operation.
Figure 15. Buffer Provides 2pF, 50pA Input Characteristics for
Fast Trigger. Amplifier-Stabilized Biasing Eliminates FET Offset
3V
2N3904
100
Q2
–5V
5V
Q1
2N5486
1.5k
330pF
U
V
TRIG
3V
INFORMATION
–
+
U
LT1394
0.01 F
LT1097
10M
C1
A1
–
+
W
0.1 F
10k
U
10M
0.1 F
OUTPUT
1394 F15
Q1 should contribute negligible timing error to minimize
overall delay. Figure 16’s photo verifies Q1’s wideband
operation. Trace B, Q1’s source, lags the input (Trace A) by
only 300ps. Input, FET buffer output and C1 output appear
as Traces A, B and C, respectively in Figure 17. As before,
the FET buffer is seen to contribute small timing error, and
C1’s output is about 8ns delayed from the input.
A = 1V/DIV
B = 1V/DIV
A = 1V/DIV
B = 1V/DIV
C = 2V/DIV
Figure 16. Trigger Buffer’s 300ps Delay Minimizes
Timing Error. 4GHz Sampling Oscilloscope’s Output Is
a Series of Dots
Figure 17. Input (Trace A), FET Source (Trace B)
and Output (Trace C) Waveforms for the Trigger.
Total Delay Is 8ns
200ps/DIV
10ns/DIV
1394 F16
LT1394
1394 F17
13