LT1394CS8#TR Linear Technology, LT1394CS8#TR Datasheet - Page 3

• Manufacturer Part Number: LT1394CS8#TR
• Description: IC COMPARATOR 7NS LOW PWR 8SOIC
• Manufacturer: Linear Technology
• Series: UltraFast™r
• Type: General Purposer

Specifications of LT1394CS8#TR

• Number Of Elements: 1
• Output Type: CMOS, Complementary, TTL
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (0.154", 3.90mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

ELECTRICAL CHARACTERISTICS
SYMBOL
V
I
I
V
V
I
t
t
t
t
t
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: This parameter is guaranteed to meet specified perforamnce
through design and characterization. It has not been tested.
Note 3: The LT1394CMS8 and LT1394CS8 are guaranteed to meet
specified performance from 0 C to 70 C and are designed, characterized
and expected to meet these extended temperature limits, but are not tested
at – 40 C and 85 C. The LT1394IS8 is guaranteed to meet the extended
temperature limits.
Note 4: Input offset voltage (V
voltages measured by forcing first one output, then the other to 1.4V.
Note 5: Input bias current (I
currents.
Note 6: Input voltage range is guaranteed in part by CMRR testing and in
part by design and characterization.
The
V
IL
+
–
PD
LPD
SU
H
PW(D)
OL
IH
IL
t
+
PD
= 5V, V
denotes specifications which apply over the full operating temperature range, otherwise specifications are T A = 25 C.
–
= – 5V, V
PARAMETER
Output Voltage Swing Low
Positive Supply Current
Negative Supply Current
LATCH Pin High Input Voltage
LATCH Pin Low Input Voltage
LATCH Pin Current
Propagation Delay (Note 7)
Differential Propagation Delay (Note 7)
Latch Propagation Delay (Note 8)
Latch Setup Time (Note 8)
Latch Hold Time (Note 8)
Minimum Disable Pulse Width
OUT
(Q) = 1.4V, V
B
) is defined as the average of the two input
OS
) is defined as the average of the two
LATCH
= V
CM
= 0V unless otherwise noted.
CONDITIONS
I
I
V
OUT
OUT
LATCH
V
V
IN
IN
= – 4mA
= – 10mA
= 100mV, V
= 100mV, V
= 0V
Note 7: t
equipment with low values of overdrive. The LT1394 is 100% tested with a
100mV step and 20mV overdrive. Correlation tests have shown that t
and t
performed to guarantee that all internal bias conditions are correct.
Propagation delay (t
V
Note 8: Latch propagation delay (t
respond when the LATCH pin is deasserted. Latch setup time (t
interval in which the input signal must remain stable prior to asserting the
latch signal. Latch hold time (t
which the input signal must remain stable.
OD
OD
OS
. Differential propagation delay is defined as:
= 5mV
= 5mV
t
PD
PD
PD
= t
limits can be guaranteed with this test, if additional DC tests are
and t
PDLH
– t
PD
PDHL
PD
cannot be measured in automatic handling
) is measured with the overdrive added to the actual
H
) is the interval after the latch is asserted in
LPD
MIN
2
) is the delay time for the output to
– 0.4
TYP
0.3
0.4
1.2
0.5
– 4
6
7
6
2
3
MAX
10.0
– 10
0.5
2.2
2.5
0.8
2.2
8.5
14
9
LT1394
SU
) is the
UNITS
PD
3
mA
mA
mA
mA
ns
ns
ns
ns
ns
ns
ns
V
V
V
V
A