EP2AGX65DF25C5 Altera Corporation, EP2AGX65DF25C5 Datasheet - Page 60

• Manufacturer Part Number: EP2AGX65DF25C5
• Description: IC ARRIA II GX FPGA 65K 572FBGA
• Manufacturer: Altera Corporation
• Series: Arria II GXr

Specifications of EP2AGX65DF25C5

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5371904
• Number Of I /o: 252
• Number Of Gates: -
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 572-FBGA
• Lead Free Status: Contains lead
• Rohs Status: RoHS non-compliant

1–52
Table 1–41. Transceiver Block Jitter Specifications for Arria II GZ Devices
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
OBSAI Receiver Jitter Tolerance
Deterministic jitter tolerance at
768 Mbps, 1536 Mbps, and
3072 Mbps
Combined deterministic and
random jitter tolerance at 768
Mbps, 1536 Mbps, and 3072
Mbps
Sinusoidal jitter tolerance at 768
Mbps
Sinusoidal jitter tolerance at
1536 Mbps
Sinusoidal jitter tolerance at
3072 Mbps
Notes to
(1) Dedicated refclk pins were used to drive the input reference clocks.
(2) The jitter numbers are valid for the stated conditions only.
(3) The jitter numbers for SONET/SDH are compliant to the GR-253-CORE Issue 3 Specification.
(4) The jitter numbers for Fibre Channel are compliant to the FC-PI-4 Specification revision 6.10.
(5) The Fibre Channel transmitter jitter generation numbers are compliant to the specification at the 
(6) The Fibre Channel receiver jitter tolerance numbers are compliant to the specification at the 
(7) The jitter numbers for XAUI are compliant to the IEEE802.3ae-2002 Specification.
(8) The jitter numbers for PCIe are compliant to the PCIe Base Specification 2.0.
(9) Arria II GZ PCIe receivers are compliant to this specification provided the V
(10) The jitter numbers for SRIO are compliant to the RapidIO Specification 1.3.
(11) The jitter numbers for GIGE are compliant to the IEEE802.3-2002 Specification.
(12) The HD-SDI and 3G-SDI jitter numbers are compliant to the SMPTE292M and SMPTE424M Specifications.
(13) The jitter numbers for Serial Attached SCSI (SAS) are compliant to the SAS-2.1 Specification.
(14) The jitter numbers for CPRI are compliant to the CPRI Specification V3.0.
(15) The jitter numbers for OBSAI are compliant to the OBSAI RP3 Specification V4.1.
Table
Description
Symbol/
1–41:
(15)
Jitter frequency = 921.6 MHz to 20
Jitter frequency = 460 MHz to 20
Jitter frequency = 1843.2 MHz to
Jitter frequency = 10.9 KHz
Jitter frequency = 21.8 KHz
Jitter frequency = 5.4 KHz
Pattern = CJPAT
Pattern = CJPAT
Pattern = CJPAT
Pattern = CJPAT
Pattern = CJPAT
Pattern = CJPAT
Pattern = CJPAT
Pattern = CJPAT
Conditions
20 MHz
MHz
MHz
TX-CM-DC-ACTIVEIDLE-DELTA
Min
(Note
–C3 and –I3
Chapter 1: Device Datasheet for Arria II Devices
> 0.37
> 0.55
Typ
R
> 8.5
> 0.1
> 8.5
> 0.1
> 8.5
> 0.1
1),
interpretability point.
of the upstream transmitter is less than 50 mV.
T
inter operability point.
(2)
Max
(Part 7 of 7)
December 2011 Altera Corporation
Min
Switching Characteristics
–C4 and –I4
> 0.37
> 0.55
Typ
> 8.5
> 0.1
> 8.5
> 0.1
> 8.5
> 0.1
Max
Unit
UI
UI
UI
UI
UI
UI
UI
UI