EP2AGX65DF25I5 Altera Corporation, EP2AGX65DF25I5 Datasheet
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Arria II Device Handbook Volume 3: Device Datasheet and Addendum Volume 3: Device Datasheet and Addendum 101 Innovation Drive San Jose, CA 95134 www.altera.com AIIGX5V3-4.2 Arria II Device Handbook Document publication date: December 2011 ...
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... Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX are Reg. U.S. Pat. & Tm. Off. and/or trademarks of Altera Corporation in the U.S. and other countries. All other trademarks and service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’ ...
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... Auto-Calibrating External Memory Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1 Connecting a Serial Configuration Device to an Arria II Device Family on AS Interface . . . . . . . . . . . 2–1 Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1 Additional Information How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1 Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1 December 2011 Altera Corporation Arria II Device Handbook Volume 3: Device Datasheet and Addendum Contents ...
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... Arria II Device Handbook Volume 3: Device Datasheet and Addendum Contents December 2011 Altera Corporation ...
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... Chapter 1. Device Datasheet for Arria II Devices Revised: Part Number: AIIGX53001-4.2 Chapter 2. Addendum for the Arria II Device Handbook Revised: Part Number: AIIGX53002-2.0 December 2011 Altera Corporation December 2011 December 2010 Arria II Device Handbook Volume 3: Device Datasheet and Addendum Chapter Revision Dates ...
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... Arria II Device Handbook Volume 3: Device Datasheet and Addendum Chapter Revision Dates December 2011 Altera Corporation ...
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... Revision History Refer to each chapter for its own specific revision history. For information on when each chapter was updated, refer to the Chapter Revision Dates section, which appears in this volume. December 2011 Altera Corporation Section I. Device Datasheet and Addendum for Arria II Devices ® ...
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... I–2 Arria II Device Handbook Volume 3: Device Datasheet and Addendum Section I: Device Datasheet and Addendum for Arria II Devices December 2011 Altera Corporation ...
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... Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX are Reg. U.S. Pat. & Tm. Off. and/or trademarks of Altera Corporation in the U.S. and other countries. All other trademarks and service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’ ...
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... Electrical Characteristics may cause permanent Minimum Maximum Unit –0.5 1.35 V –0.5 1.8 V –0.5 3.75 V –0.5 3.75 V –0.5 3.9 V –0.5 1.35 V –0.5 3.75 V –0.5 4.0 V – — 3.75 V — 1.21 V — 1.8 V –55 125 °C –65 150 °C Minimum Maximum Unit -0.5 1.35 V -0.5 1.8 V -0.5 3.75 V -0.5 3.75 V -0.5 3.75 V -0.5 3.75 V -0.5 3.9 V -0.5 3.75 V -0.5 1.35 V -0.5 3.75 V -0.5 4 December 2011 Altera Corporation ...
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... A DC signal is equivalent to 100% duty cycle. For example, a signal that overshoots to 4.3 V can only be at 4.3 V for 5.41% over the lifetime of the device; for a device lifetime of 10 years, this amounts to 5.41/10ths of a year. December 2011 Altera Corporation Description Arria II Device Handbook Volume 3: Device Datasheet and Addendum 1– ...
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... AC Input Voltage 4.3 4.35 4.4 4.45 4.5 4.55 4.6 I/O Standard Chapter 1: Device Datasheet for Arria II Devices Electrical Characteristics Overshoot Duration Unit High Time 100.000 % 79.330 % 46.270 % 27.030 % 15.800 % 9.240 % 5.410 % 3.160 % 1.850 % 1.080 % 0.630 % 0.370 % 0.220 % I/O Frequency (MHz) 333 400 333 260 250 200 December 2011 Altera Corporation ...
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... Supplies power to the transceiver PMA V CCA regulator Supplies power to the transceiver PMA TX, V CCL_GXB PMA RX, and clocking Supplies power to the transceiver PMA V CCH_GXB output (TX) buffer T Operating junction temperature J December 2011 Altera Corporation . RAMP (Note 1) (Part Condition Minimum — 0.87 — 1.425 — 1.2 — 3.135 — ...
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... Typical Maximum 0.87 0.90 0.93 1.45 1.50 1.55 2.375 2.5 2.625 2.85 3.0 3.15 2.375 2.5 2.625 2.85 3.0 3.15 2.375 2.5 2.625 1.71 1.8 1.89 1.425 1.5 1.575 1.14 1.2 1.26 2.85 3.0 3.15 2.375 2.5 2.625 1.71 1.8 1.89 2.375 2.5 2.625 0.87 0.90 0.93 2.375 2.5 2.625 1.2 — 3.3 –0.5 — 3.6 0 — V CCIO 3.0/2.5 (4) 3.15/2.625 0.87 0.9 0.93 1.05 1.1 1.15 1.05 1.1 1.15 1.05 1.1 1.15 1.05 1.1 1.15 December 2011 Altera Corporation Unit ...
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... I/O Pin Leakage Current Table 1–7 lists the Arria II GX I/O pin leakage current specifications. Table 1–7. I/O Pin Leakage Current for Arria II GX Devices Symbol I Input pin I I Tri-stated I/O pin OZ December 2011 Altera Corporation (Note 6) Condition Minimum — — — — Commercial Industrial Normal POR ...
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... Min Max Min Max Min Max 50 — 70 — 70 — –50 — –70 — –70 — — 300 — 500 — 500 — –300 — –500 — –500 0.7 1.7 0.8 2 0.8 2 December 2011 Altera Corporation Unit µA µA µA µA V ...
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... OCT S 1.8 without calibration 25- R 25- series OCT S 1.5, 1.2 without calibration 50- R 50- series OCT S 1.5, 1.2 without calibration 25- 25- series OCT 3.0, 2.5, 1.8, 1.5, with calibration 1.2 December 2011 Altera Corporation V (V) CCIO 1.2 1.5 1.8 Max Min Max Min Max — 25.0 — 30.0 — — -25.0 — ...
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... Conditions ( 3.0, 2.5, CCIO ± 8 1.8, 1.5, 1 3.0, 2.5, CCIO ± 8 1.8, 1.5, 1 2.5, 1.8, CCIO ± 10 1.5, 1 3.0, 2.5, CCIO ± 10 1.8, 1.5, 1 3.0, 2.5, CCIO ± 10 1.8, 1.5, 1.2 Electrical Characteristics (Note 1) (Part Unit Industrial ± ± (Note 1) Unit C3,I3 C4,I4 ± 8 ± ± 8 ± ± 10 ± ± 10 ± ± 10 ± December 2011 Altera Corporation ...
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... When voltage and temperature conditions change after calibration, the resistance may change. Use Equation 1–1 voltage and temperature vary after power-up calibration for Arria II GX and GZ devices. Equation 1–1. OCT Variation Notes to Equation (1) R value calculated from OCT V . CCIO December 2011 Altera Corporation Resistance Tolerance Conditions (V) C3, 3.0, 2.5 ± 40 CCIO V = 1.8, 1.5 ± 40 CCIO V = 1.2 ± ...
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... Description Chapter 1: Device Datasheet for Arria II Devices Electrical Characteristics at power up. CCIO dR/dV (%/mV) 0.035 0.039 0.086 0.136 0.288 (Note 1) dR/dV (%/mV) 0.0297 0.0344 0.0499 0.0744 0.1241 Typical Unit 7 pF December 2011 Altera Corporation ...
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... All I/O pins have an option to enable weak pull-up except configuration, test, and JTAG pins. The weak pull-down feature is only available for JTAG TCK. (2) Pin pull-up resistance values may be lower if an external source drives the pin higher than V December 2011 Altera Corporation Description Conditions ...
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... Electrical Characteristics Typ Max Unit 25 — k 25 — k 25 — k 25 — k 25 — k . (Note 1) Maximum 300 (2) 100 dv/dt, in which “C” is I/O pin IOPIN range for CCIO Minimum Unit 220 mV 180 mV 110 December 2011 Altera Corporation ...
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... Min Typ Max LVTTL 2.85 3 3.15 LVCMOS 2.85 3 3.15 2.5 V 2.375 2.5 2.625 1.8 V 1.71 1.8 1.89 1.5 V 1.425 1.5 1.575 December 2011 Altera Corporation Table 1–35 list input voltage (V and V IH and and V values are valid at the corresponding Table 1–22 through V ( Min Max Min Max – ...
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... Max 0.51 × REF REF V REF V 0.04 0.04 CCIO REF REF 0.969 V REF 0.04 0.04 0.53 × 0.47 × 0.53 × V REF CCIO CCIO CCIO 0.95 — — CCIO 0.9 — — CCIO 0.53 × — — CCIO V CCIO December 2011 Altera Corporation I OH (mA) -2 -0.5 -0 ...
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... Table 1–27. Single-Ended SSTL and HSTL I/O Standards Signal Specifications for Arria II GZ Devices (Part (V) IL(DC) I/O Standard Min Max V REF SSTL-2 Class I -0.3 0.15 V REF SSTL-2 Class II -0.3 0.15 V REF SSTL-18 Class I -0.3 0.125 V REF SSTL-18 Class II -0.3 0.125 V REF SSTL-15 Class I — 0.1 December 2011 Altera Corporation V (V) V (V) V IH(DC) IL(AC) IH(AC) Min Max Max - REF CCIO V - 0.35 REF 0.18 0 REF CCIO ...
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... Typ CCIO CCIO CCIO 0.62 — + 0.2 + 0 CCIO CCIO CCIO + 0.5 — + 0.6 - 0.125 0.175 V CCIO — 0.35 — — 2 December 2011 Altera Corporation I OH (mA) -16 -8 -16 -8 -16 -8 -16 (V) Max V /2 CCIO + 0. CCIO + 0.125 / — (V) Max V /2 CCIO + 0. CCIO + 0.125 / ...
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... range: 90 <= RL <= 110 (4) The RSDS and mini-LVDS I/O standards are only supported for differential outputs. (5) The LVPECL input standard is supported at the dedicated clock input pins (GCLK) only. December 2011 Altera Corporation V (V) V (V) DIF(DC) X(AC) Max Min ...
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... II PowerPlay Power Analyzer feature and the PowerPlay Power Analysis Electrical Characteristics (V) (3) V (V) (3) OCM Typ Max Min Typ Max — 0.6 1.125 1.25 1.375 — 0.6 1 1.25 1.5 0.2 0.6 0.5 1.2 1.4 0.2 0.6 0.5 1.2 1.5 — 0.6 1 1.2 1.4 — 0.6 1 1.2 1.5 — — — — — 1–21. PowerPlay Early Power chapter in volume 3 of the December 2011 Altera Corporation ...
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Switching Characteristics This section provides performance characteristics of the Arria II GX and GZ core and periphery blocks for commercial grade devices. The following tables are considered final and are based on actual silicon characterization and testing. These numbers reflect ...
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Table 1–34. Transceiver Specifications for Arria II GX Devices Symbol/ Condition Description Min Spread-spectrum PCIe — downspread –0.5% On-chip termination — — resistors V ICM — 1100 ± 5% (AC coupled) HCSL I/O standard for V ICM PCIe 250 (DC ...
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Table 1–34. Transceiver Specifications for Arria II GX Devices Symbol/ Condition Description Min PCIe fixedclk clock Receiver — frequency Detect Dynamic 2.5/ reconfig_ reconfig. clk clock 37.5 clock frequency (4) frequency Delta time between — — reconfig_ (5) clks Transceiver ...
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Table 1–34. Transceiver Specifications for Arria II GX Devices Symbol/ Condition Description Min Minimum peak-to-peak differential input — 100 voltage V (diff ID p- 0.82 V ICM — setting V ICM V =1.1 V ICM — 1100 setting ...
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Table 1–34. Transceiver Specifications for Arria II GX Devices Symbol/ Condition Description Min LTD lock time — 0 (11) Data lock time from rx_ — — freqlocked (12) DC Gain — Setting = 0 Programmable DC Gain — DC gain ...
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Table 1–34. Transceiver Specifications for Arria II GX Devices Symbol/ Condition Description Min Intra- differential pair — — skew Intra-transceiver PCIe ×4 — block skew Inter-transceiver PCIe ×8 — block skew CMU PLL0 and CMU PLL1 CMU PLL lock time ...
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Table 1–34. Transceiver Specifications for Arria II GX Devices Symbol/ Condition Description Min Digital reset — pulse width Notes to Table 1–34: (1) For AC-coupled links, the on-chip biasing circuit is switched off before and during configuration. Ensure that input ...
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... December 2011 Altera Corporation ...
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... Equalization = 0 opening at receiver serial DC gain = 0 dB input pins (8) Data Rate > 5 Gbps Equalization = 0 DC gain = 0.82 V ICM setting V ICM V = 1.1 V setting ICM December 2011 Altera Corporation –C3 and –I3 (1) Min Typ Max — 10 — 125 — 125 — 2.5/ 37.5 — 50 (4) — ...
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... MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz recon fig_ — — 17000 clk cycles — 0 — dB — 3 — dB — 6 — dB December 2011 Altera Corporation ...
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... Example: PCIe ×8, channel-to-channel skew Basic ×8 CMU0 PLL and CMU1 PLL Supported Data Range pll_powerdown minimum pulse width (tpll_powerdown) CMU PLL lock time from pll_powerdown de-assertion December 2011 Altera Corporation –C3 and –I3 (1) Min Typ Max 1.5-V PCML — 600 — 6375 — ...
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... Unit Min Typ Max MHz MHz MHz MHz MHz 3 - 5.5 MHz 3 - 5.5 MHz MHz MHz MHz 3 MHz 25 — 250 MHz — Figure 1–1 on page 1–33. Figure 1–1 on page 1–33. Figure 1–2 on page 1–33. Transceiver December 2011 Altera Corporation ...
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... CDR LTR Time Figure 1–2 shows the lock time parameters in automatic mode. Figure 1–2. Lock Time Parameters for Automatic Mode CDR status r x_freqlocked r x_dataout December 2011 Altera Corporation LTR LTD lock time CDR Minimum T1b LTR Invalid data Data lock time from rx_freqlocked Arria II Device Handbook Volume 3: Device Datasheet and Addendum 1– ...
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... Chapter 1: Device Datasheet for Arria II Devices Switching Characteristics Positive Channel (p) Negative Channel (n) Ground p − Positive Channel (p) Negative Channel (n) Ground p − Setting (mV 595 ± 680 ± 765 ± 850 ± 1020 ± 20% 20% 20% 20% 20% December 2011 Altera Corporation 7 ...
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... Setting 0 (off 0.7 2 2.7 3 4.9 4 7.5 5 — 6 — December 2011 Altera Corporation for TX term that equals 100 . for Arria II GX and GZ OD Setting, TX Termination = 100 for Arria II Devices OD Quartus II Setting (Arria II GZ Table 1–38 are a representation of possible ...
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... Table 1–39 Arria II HSSI HSPICE models. V Setting 0 0 0.7 0.3 0 1.2 0.5 0.3 1.3 0.8 0.5 1.8 1.1 0.7 2.1 1.3 0.9 2.4 1.6 1.2 2.8 1.9 1.4 3.2 2.2 1.7 3.5 2.6 1.9 3.8 2.8 2.1 4.2 3.1 2.3 4.5 3.4 2.6 4.9 3.7 2.9 5.3 4 3.1 5.7 4.4 3.4 6.1 4.7 3.6 6.6 5 5.4 4.3 8 6.1 4.8 9 6.8 5.4 10 7.6 6 11.4 8.4 6.8 12.6 9.4 7.4 N/A 10.3 8.1 N/A 11.3 8.8 Switching Characteristics are a representation 0 0.4 0.2 0 0.6 0.3 0 0.8 0.5 0.2 1 0.7 0.3 1.2 0.9 0.4 1.4 1.1 0.6 1.6 1.2 0.6 1.7 1.3 0.7 1.9 1.5 0.8 2.2 1.7 0.9 2.4 1.8 1.1 2.6 2 1.2 2.8 2.2 1.4 3.1 2.4 1.5 3.3 2.7 1.7 3 4.3 3.4 2.3 4.8 3.9 2.6 5.4 4.4 3 5.9 4.9 3.3 6.4 5.3 3.6 7.1 5.8 4 December 2011 Altera Corporation ...
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... Mbps RMS jitter at Pattern = 2488.32 Mbps PRBS15 SONET/SDH Receiver Jitter Tolerance Jitter frequency = 0.03 KHz Pattern = PRBS15 Jitter frequency = Jitter tolerance at 25 KHZ 622.08 Mbps Pattern = PRBS15 Jitter frequency = 250 KHz Pattern = PRBS15 December 2011 Altera Corporation V Setting N/A 12.5 9.6 N/A N/A 11.4 N/A N/A 12.9 (Note 1) ...
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... C5 Min Typ Max Min Typ > 15 > 15 > 1.5 > 1.5 > 0.15 > 0.15 > 0.15 > 0.15 — — 0.3 — — — — 0.17 — — > 0.65 > 0.65 > 0.37 > 0.37 > 8.5 > 8.5 > 0.1 > 0.1 > 0.1 > 0.1 — — 0.25 — — December 2011 Altera Corporation Unit Max 0 0.25 UI ...
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... Gbps (peak-to-peak) Pattern = CJPAT Jitter frequency = 20 MHz Data rate = 1.25, 2.5, 3.125 Gbps Pattern = CJPAT GIGE Transmit Jitter Generation (6) Deterministic jitter Pattern = CRPAT (peak-to-peak) December 2011 Altera Corporation (Note Min Typ Max Min Typ Max > 0.6 > 0.6 (9) 65 — ...
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... December 2011 Altera Corporation Unit Max 0.279 — UI — UI — UI — UI — UI — UI — UI ...
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... Sinusoidal jitter Data rate = tolerance 2.97 Gbps (3G) (peak-to-peak) Pattern = single line scramble color bar Jitter frequency = 148.5 MHz Data rate = 2.97 Gbps (3G) Pattern = single line scramble color bar December 2011 Altera Corporation (Note Min Typ Max Min Typ Max 0.2 — — 0.2 — ...
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... December 2011 Altera Corporation Unit Max 0.55 UI 0.35 UI 0.55 UI 0.35 UI — UI — kHz ...
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... Gbps (G3) SSC modulation Compliance deviation at pattern 6.0 Gbps (G3) RX differential Compliance skew at 6.0 Gbps pattern (G3 common Compliance mode voltage at pattern 6.0 Gbps (G3) December 2011 Altera Corporation (Note Min Typ Max Min Typ Max 5700 5700 80 80 150 150 > 0.65 > 0.65 > 0.35 > ...
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... December 2011 Altera Corporation Unit Max 0.279 UI 0.35 UI 0. 0.35 UI 0.17 UI ...
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... Mbps 460.8 KHz to 20 MHz Pattern = CJPAT Jitter frequency = 10.9 KHz Pattern = CJPAT Sinusoidal jitter tolerance at Jitter frequency = 1536 Mbps 921.6 KHz to 20 MHz Pattern = CJPAT December 2011 Altera Corporation (Note Min Typ Max Min Typ Max > 0.37 > 0.37 > 0.55 > 0.55 > 8.5 > ...
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... Typ Max Min Typ — 0.1 — — — 0.01 — — — 0.1 — — — 0.01 — — > 15 > 15 > 1.5 > 1.5 > 0.15 > 0.15 December 2011 Altera Corporation Unit Max UI UI Unit Max 0.1 UI 0.01 UI 0 ...
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... XAUI Transmit Jitter Generation (7) Total jitter at 3.125 Gbps Deterministic jitter at 3.125 Gbps XAUI Receiver Jitter Tolerance (7) Total jitter Deterministic jitter December 2011 Altera Corporation (Note Conditions Min Jitter frequency = 0.06 KHz Pattern = PRBS15 Jitter frequency = 100 KHZ Pattern = PRBS15 Jitter frequency = 1 MHz ...
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... Not supported — 175 65 — — 0.17 — — — 0.35 — — > 0.37 > 0.37 > 0.55 > 0.55 > 8.5 > 8.5 > 0.1 > 0.1 > 0.1 > 0.1 — 0.14 — — — 0.279 — — December 2011 Altera Corporation Unit Max 0.25 UI — 175 UI 0. 0.14 UI 0.279 UI ...
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... CEI Receiver Jitter Tolerance Deterministic jitter tolerance (peak-to-peak) Pattern = PRBS31 BER = 10 Combined deterministic and random jitter tolerance (peak-to- Pattern = PRBS31 BER = 10 peak) December 2011 Altera Corporation (Note Conditions Min Pattern = CJPAT Pattern = CJPAT Data rate = 3.75 Gbps — Pattern = CJPAT Data rate = 3.75 Gbps — ...
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... December 2011 Altera Corporation Unit Max — UI — UI — UI — UI — 0.55 UI 0.35 UI 0.55 UI ...
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... Combined deterministic and random jitter tolerance OBSAI Transmit Jitter Generation (15) Total jitter at 768 Mbps, 1536 Mbps, and 3072 Mbps Deterministic jitter at 768 MBps, 1536 Mbps, and 3072 Mbps December 2011 Altera Corporation (Note –C3 and –I3 Conditions Min Pattern = CJPAT — Pattern = CJPAT — ...
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... Typ Max Min Typ > 0.37 > 0.37 > 0.55 > 0.55 > 8.5 > 8.5 > 0.1 > 0.1 > 8.5 > 8.5 > 0.1 > 0.1 > 8.5 > 8.5 > 0.1 > 0.1 inter operability point. T interpretability point the upstream transmitter is less than 50 mV. December 2011 Altera Corporation Unit Max ...
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... External feedback clock input duty cycle EINDUTY Input clock cycle-to-cycle jitter (Frequency 100 MHz) t (3), INCCJ Input clock cycle-to-cycle jitter (Frequency 100 MHz) (4) December 2011 Altera Corporation Performance I3, C4 C5,I5 500 500 420 350 Performance –C3 and –I3 ...
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... SCANCLK — 3.5 — cycles SCANCLK — 1 — cycles — — 100 MHz — — — — — 0.3 — MHz — 1.5 — MHz — 4 — MHz — — ± — — ns December 2011 Altera Corporation ...
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... Time required to reconfigure phase shift CONFIGPHASE f scanclk frequency SCANCLK Time required to lock from end-of-device configuration or t LOCK de-assertion of areset December 2011 Altera Corporation Description the PLL. MAX OUT –12 (14 sigma, 99.99999999974404% confidence level). The output jitter specification applies Table 1–62 on page 1– ...
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... MHz 1.5 — MHz 4 — MHz — ±50 ps — — ns — 0.15 UI (p-p) — ±750 ps (p-p) — 175 ps (p-p) — 17.5 mUI (p-p) — 175 ps (p-p) — 17.5 mUI (p-p) — 600 ps (p-p) — 60 mUI (p-p) — 600 ps (p-p) — 60 mUI (p-p) — 250 ps (p-p) — 25 mUI (p-p) — ±10 % Table 1–63 on December 2011 Altera Corporation ...
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... December 2011 Altera Corporation (Note 1) Resources Performance Used Number Multipliers 1 ...
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... MHz 500 450 378 MHz 400 360 310 MHz 280 250 210 MHz 400 360 310 MHz 280 250 210 MHz 400 360 310 MHz 280 250 210 MHz 850 950 1130 ps 690 770 920 ps December 2011 Altera Corporation ...
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... To achieve the maximum memory block performance, use a memory block clock that comes through global clock routing from an on-chip PLL set to 50% output duty cycle. Use the Quartus II software to report timing for this and other memory block clocking schemes. (2) When you use the error detection CRC feature, there is no degradation in F December 2011 Altera Corporation Resources Used Performance ...
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... MHz MHz 8 MHz — — 10 MHz Min Max Unit 30 — — — — — — ns — — — Min Typ Max Unit s 500 — — December 2011 Altera Corporation ...
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... I/O f HSCLK_IN Clock boost (input clock factor frequency)– (1) Column I/O f HSCLK_OUT (output clock — frequency)–Row I/O f HSCLK_OUT (output clock — frequency)– Column I/O December 2011 Altera Corporation I3 C4 Min Max Min Max 5 670 5 670 5 500 5 500 5 670 5 670 5 500 5 500 ...
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... Chapter 1: Device Datasheet for Arria II Devices Switching Characteristics C5,I5 C6 Unit Min Max Min Max 1050 150 150 840 Mbps (2) (3) 840 (3) 740 Mbps (3) (3) (3) (3) Mbps (3) 840 (3) 740 Mbps December 2011 Altera Corporation ...
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... RISE FALL LVDS_E_3R True LVDS (5) TCCS Emulated LVDS_E_3R Receiver (6) True differential I/O standards - SERDES factor f (data HSDRDPA rate) December 2011 Altera Corporation I3 C4 Min Max Min Max — 175 — 175 — 0.105 — 0.105 — 260 — 260 — ...
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... Mbps (3) (7) (3) (7) Mbps PPM — 300 — 300 — 10,000 — 10,000 UI — 350 — 400 ps (Part C4, I4 Unit Min Typ Max 5 — 717 MHz 5 — 717 MHz 5 — 420 MHz 5 — 717 (7) MHz December 2011 Altera Corporation ...
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... True differential I/O standards Emulated differential I/O standards with three external output t t RISE & FALL resistor networks Emulated differential I/O standards with one external output resistor December 2011 Altera Corporation (Note 1), (2), (10) (Part C3, I3 Min Typ Max Min (4) — 1250 (4) (4) — ...
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... Switching Characteristics C4, I4 Unit Typ Max — 100 ps — 250 ps — 1250 Mbps — (6) Mbps — (5) Mbps — (5) Mbps — 10000 UI — 300 ± PPM — 300 ps Maximum (4) 640 data transitions 640 data transitions 640 data transitions December 2011 Altera Corporation ...
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... Arria II GZ devices at a data rate less than 1.25 Gbps and all the Arria II GX devices. Figure 1–5. LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specification for All Arria II GX Devices and for Arria II GZ Devices at a Data Rate less than 1.25 Gbps Sinusoidal Jitter Amplitude (UI) 0.1 P-P December 2011 Altera Corporation (Note 1), (2), (3) Number of Data Transitions in One ...
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... Chapter 1: Device Datasheet for Arria II Devices Switching Characteristics Jitter Frequency (Hz) 50,000,000 (F4) Sinusoidal Jitter (UI) 25.000 25.000 0.350 0.350 DQS Delay Number of Buffer Mode (°) Delay Chains (1) 22.5 Low 16 30 Low 12 36 Low 10 45 Low 8 30 High 12 December 2011 Altera Corporation ...
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... The valid settings for phase offset are -64 to +63 for frequency modes and -32 to +31 for frequency modes (2) The typical value equals the average of the minimum and maximum values. (3) The delay settings are linear. December 2011 Altera Corporation Resolution I3, C5 ...
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... DQS_PSERR I3, C5 Unit 108 ps 120 144 ps ) for Arria II GZ DQS_PSERR –4 Unit 120 ps (Note 1), (2), (3) –5 –6 Unit Max Min Max 125 -125 125 ps 250 -250 250 ps 125 -125 125 ps December 2011 Altera Corporation ...
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... Table 1–65. Duty Cycle Distortion on I/O Pins for Arria II GZ Devices Symbol Output Duty Cycle Note to Table 1–65: (1) The DCD specification applies to clock outputs from the PLL, global clock tree, IOE driving dedicated, and general purpose I/O pins. December 2011 Altera Corporation (Note 1), (2), –3 Symbol Min Max t ...
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... Slow Model Unit 0.801 0.857 0.864 ns 0.371 0.407 0.405 ns 2.948 3.157 3.178 ns 0.889 0.952 0.959 ns 0.817 0.875 0.882 ns 0.321 0.345 0.347 ns December 2011 Altera Corporation ...
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... Quartus II timing analyzer provides a more accurate and precise I/O timing data based on the specifics of the design after place-and-route is complete. f The Microsoft Excel-based I/O Timing spreadsheet is downloadable from the Literature: Arria II Devices December 2011 Altera Corporation web page. Arria II Device Handbook Volume 3: Device Datasheet and Addendum 1–73 ...
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... Arria II Device Handbook Volume 3: Device Datasheet and Addendum Chapter 1: Device Datasheet for Arria II Devices Definitions Glossary Positive Channel ( Negative Channel ( Ground p − Positive Channel ( Negative Channel ( Ground p − December 2011 Altera Corporation ...
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... M, PLL Core Clock Specifications Note: (1) CoreClock can only be fed by dedicated clock input pins or PLL outputs Receiver differential input discrete resistor (external to the Arria II device December 2011 Altera Corporation Definitions t JCP JCH JCL JPSU t t JPZX JPCO Switchover ...
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... RISE Arria II Device Handbook Volume 3: Device Datasheet and Addendum Definitions Bit Time Sampling Window RSKM 0.5 x TCCS (SW REF V OL Chapter 1: Device Datasheet for Arria II Devices Glossary RSKM 0.5 x TCCS V CCIO IH(DC) V IL(DC) V IL( variation and CO /w) C December 2011 Altera Corporation ...
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... Updated Table 1–32, Table 1–33, Table 1–38, Table 1–41, and Table 1–61. ■ June 2011 4.1 Updated the “Switching Characteristics” section introduction. ■ Minor text edits. ■ December 2011 Altera Corporation Definitions Changes Table 1–32, Table 1–33, Table 1–34, 1–54, and Table 1– ...
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... Added Table 1–32. ■ Updated Equation 1–1. ■ March 2009 1.1 Added “I/O Timing” section. February 2009 1.0 Initial release. Arria II Device Handbook Volume 3: Device Datasheet and Addendum Chapter 1: Device Datasheet for Arria II Devices Document Revision History Changes December 2011 Altera Corporation ...
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... Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX are Reg. U.S. Pat. & Tm. Off. and/or trademarks of Altera Corporation in the U.S. and other countries. All other trademarks and service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’ ...
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... Arria II Device Handbook Volume 3: Device Datasheet and Addendum Chapter 2: Addendum for the Arria II Device Handbook Document Revision History December 2010 Altera Corporation ...
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... The following table shows the typographic conventions this document uses. Visual Cue Bold Type with Initial Capital Letters bold type Italic Type with Initial Capital Letters italic type Initial Capital Letters “Subheading Title” December 2011 Altera Corporation (1) Contact Method Website Website Email Website Email Email ...
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... A warning calls attention to a condition or possible situation that can cause you injury. The envelope links to the Email Subscription Management Center website, where you can sign up to receive update notifications for Altera documents. Additional Information Typographic Conventions page of the Altera December 2011 Altera Corporation ...