EP4SE820H40C4 Altera Corporation, EP4SE820H40C4 Datasheet - Page 14
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EP4SE820H40C4
Manufacturer Part Number
EP4SE820H40C4
Description
IC STRATIX IV FPGA 820K 1517HBGA
Manufacturer
Altera Corporation
Series
STRATIX® IV Er
Datasheet
1.EP4SGX70DF29C4N.pdf
(80 pages)
Specifications of EP4SE820H40C4
Number Of Logic Elements/cells
813050
Number Of Labs/clbs
32522
Total Ram Bits
34093056
Number Of I /o
976
Number Of Gates
-
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1517-BBGA Exposed Pad
Lead Free Status
Contains lead
Rohs Status
RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Electrical Characteristics
Table 1–6. Transceiver Power Supply Operating Conditions for Stratix IV GX Devices (Part 2 of 2)
Table 1–7. Transceiver Power Supply Operating Conditions for Stratix IV GT Devices
December 2011 Altera Corporation
V
V
V
V
V
V
Notes to
(1) Transceiver power supplies do not have power-on-reset (POR) circuitry. After initial power-up, violating the transceiver power supply operating
(2) V
(3) n = 0, 1, 2, or 3.
(4) V
V
V
V
V
V
V
V
V
V
V
V
V
Notes to
(1) For the recommended operating conditions for Stratix IV GT engineering sample (ES1) devices, contact your local Altera sales representative.
(2) Transceiver power supplies do not have power-on-reset circuitry. After initial power-up, violating the transceiver power supply operating
(3) n = 0, 1, 2, or 3.
CCT_L
CCT_R
CCL_GXBLn
CCL_GXBRn
CCH_GXBLn
CCH_GXBRn
CCA_L
CCA_R
CCHIP_L
CCHIP_R
CCR_L
CCR_R
CCT_L
CCT_R
CCL_GXBLn
CCL_GXBRn
CCH_GXBLn
CCH_GXBRn
conditions could lead to unpredictable link behavior.
or both, are configured at a base data rate > 4.25 Gbps. For data rates up to 4.25 Gbps, you can connect V
connect V
conditions could lead to unpredictable link behavior.
CCA_L/R
CCH_GXBL/R
Symbol
Symbol
Table
Table
(3)
(3)
must be connected to a 3.0-V supply if the clock multiplier unit (CMU) phase-locked loop (PLL), receiver clock data recovery (CDR),
(3)
(3)
(3)
(3)
(3)
(3)
CCH_GXBL/R
1–6:
1–7:
must be connected to a 1.4-V supply if the transmitter channel data rate is > 6.5 Gbps. For data rates up to 6.5 Gbps, you can
Transmitter power (left side)
Transmitter power (right side)
Transceiver clock power (left side)
Transceiver clock power (right side)
Transmitter output buffer power (left side)
Transmitter output buffer power (right side)
Transceiver high voltage power (left side)
Transceiver high voltage power (right side)
Transceiver HIP digital power (left side)
Transceiver HIP digital power (right side)
Receiver power (left side)
Receiver power (right side)
Transmitter power (left side)
Transmitter power (right side)
Transceiver clock power (left side)
Transceiver clock power (right side)
Transmitter output buffer power (left side)
Transmitter output buffer power (right side)
to either 1.4 V or 1.5 V.
Table 1–7
transceiver power supply.
DC Characteristics
This section lists the supply current, I/O pin leakage current, bus hold, on-chip
termination (OCT) tolerance, input pin capacitance, and hot socketing specifications.
lists the recommended operating conditions for the Stratix IV GT
Description
Description
Stratix IV Device Handbook Volume 4: Device Datasheet and Addendum
1.33/1.425 1.4/1.5
Minimum
Minimum
1.045
1.045
3.17
3.17
0.92
0.92
1.15
1.15
1.15
1.15
1.15
1.15
1.33
1.33
1.05
1.05
(Note
Typical
Typical
0.95
0.95
1.1
1.1
1.1
1.1
CCA_L/R
3.3
3.3
1.2
1.2
1.2
1.4
1.4
1.2
1.2
1.2
1),
(4)
(2)
to either 3.0 V or 2.5 V.
(Note 1)
1.47/1.575
Maximum
Maximum
1.155
1.155
1.15
1.15
3.43
3.43
0.98
0.98
1.25
1.25
1.25
1.25
1.25
1.25
1.47
1.47
Unit
Unit
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
1–6