STM8L151C6 STMicroelectronics, STM8L151C6 Datasheet - Page 49

• Manufacturer Part Number: STM8L151C6
• Description: STM8L-Ultra Low Power-8 bits Microcontrollers
• Manufacturer: STMicroelectronics

Specifications of STM8L151C6

• Temp. Range: - 40 °C to 85, 105 or 125 °C
• 5 Low Power Modes: Wait, Low power run (5.1 μA), Low power wait (3 μA), Active-halt with full RTC (1.3 μA), Halt (350 nA)
• Consumption: 195 μA/MHz+440μA
• Ultralow Leakage Per I/0: 50 nA
• Fast Wakeup From Halt: 4.7 μs
• Lcd: up to 4x28 segments w/ step-up converter
• 4 Channels; Supported Peripherals: ADC, DAC, SPI, I2C, USART, timers
• 2 Watchdogs: 1 Window, 1 Independent

STM8L151xx, STM8L152xx
Table 9.
0x00 53AE to
0x00 538A to
to 0x00 538F
0x00 5352 to
to 0x00 5383
0x00 5386 to
0x00 5391 to
0x00 53AC
0x00 53AD
0x00 534E
0x00 538B
0x00 538C
0x00 538D
0x00 538E
0x00 53AB
0x00 53FF
0x00 534F
0x00 5350
0x00 5351
0x00 537F
0x00 5380
0x00 5381
0x00 5382
0x00 5384
0x00 5385
0x00 5387
0x00 5388
0x00 5389
0x00 5390
Address
General hardware register map (continued)
Block
ADC1
DAC
DAC_SWTRIGR
ADC1_TRIGR1
ADC1_TRIGR2
ADC1_TRIGR3
ADC1_TRIGR4
Register label
DAC_RDHRH
DAC_RDHRL
DAC_LDHRH
DAC_LDHRL
DAC_DORH
DAC_DORL
DAC_DHR8
DAC_CR1
DAC_CR2
DAC_SR
Doc ID 15962 Rev 9
Reserved area (46 bytes)
Reserved area (82 bytes)
DAC right aligned data holding register low
DAC left aligned data holding register high
DAC left aligned data holding register low
DAC right aligned data holding register
Reserved area (27 bytes)
Reserved area (2 bytes)
Reserved area (2 bytes)
Reserved area (2 bytes)
Reserved area (2 bytes)
DAC 8-bit data holding register
DAC data output register high
DAC software trigger register
DAC data output register low
ADC1 trigger disable 1
ADC1 trigger disable 2
ADC1 trigger disable 3
ADC1 trigger disable 4
DAC control register 1
DAC control register 2
DAC status register
Register name
high
Memory and register map
status
Reset
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
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