STM32TS60 STMicroelectronics, STM32TS60 Datasheet - Page 9

• Manufacturer Part Number: STM32TS60
• Description: Multi-touch screen controller
• Manufacturer: STMicroelectronics

Specifications of STM32TS60

• Core: ARM 32-bit CortexTM-M3 CPU
• Conversion Range: 0 to 3.6 V
• Peripherals Supported: timers, ADC, SPIs, I2Cs, USART, PMSE and PMAD.
• Systick Timer: a 24-bit downcounter

STM32TS60
2.2
2.2.1
2.2.2
2.2.3
2.2.4
2.2.5
Peripheral overview
ARM Cortex-M3 core with embedded Flash and SRAM
The ARM Cortex-M3 processor is the latest generation of ARM processors for embedded
systems. It has been developed to provide a low-cost platform that meets the needs of MCU
implementation, with a reduced pin count and low power consumption, while delivering
outstanding computational performance and an advanced system response to interrupts.
The ARM Cortex-M3 32-bit RISC processor features exceptional code efficiency, delivering
the high performance expected from an ARM core in the memory size usually associated
with 8- and 16-bit devices.
The STM32TS60 device, having an embedded ARM core, is therefore compatible with all
ARM tools and software.
Figure 1
Embedded Flash memory
32 Kbytes of embedded Flash is available for storing programs and data.
CRC (cyclic redundancy check) calculation unit
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit
data word and a fixed generator polynomial.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at
link-time and stored at a given memory location.
Embedded SRAM
The 10 Kbytes of embedded SRAM can be accessed (read/write) at CPU clock speed with 0
wait states.
Nested vectored interrupt controller (NVIC)
The STM32TS60 embeds a nested vectored interrupt controller which can handle up to 43
maskable interrupt channels (not including the 16 interrupt lines of Cortex-M3) and 16
priority levels. Features include:
●
●
●
●
●
●
●
●
Closely coupled NVIC which gives low-latency interrupt processing
Interrupt entry vector table address which is passed directly to the core
Closely coupled NVIC core interface
Early processing of interrupts is allowed
Processing of “late arriving” higher priority interrupts
Support for tail-chaining
Processor state is automatically saved
Interrupt entry is restored on interrupt exit with no instruction overhead
shows the general block diagram of the device family.
Doc ID 16925 Rev 3
Description
9/27