STR911FAW42 STMicroelectronics, STR911FAW42 Datasheet - Page 71

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STR911FAW42

Manufacturer Part Number
STR911FAW42
Description
32-bit MCU
Manufacturer
STMicroelectronics
Datasheet

Specifications of STR911FAW42

Arm966e-s Risc Core
Harvard architecture, 5-stage pipeline, Tightly-Coupled Memories (SRAM and Flash)

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STR91xFAxxx
Table 25.
1.
Bank erase
Sector erase
Bank program
Sector program
Word program
V
DD
= 1.8 V, V
Flash memory program/erase characteristics (Flash size = 1 MB / 2 MB)
Table 26.
DDQ
Program/erase cycles
Data retention
= 3.3 V
Primary bank (2 Mbytes)
Primary bank (1 Mbytes)
Secondary bank (128 Kbytes)
Of primary bank (64 Kbytes)
Of secondary bank (16 Kbytes)
Primary bank (2 Mbytes)
Primary bank (1 Mbytes)
Secondary bank (128 Kbytes)
Of primary bank (64 Kbytes)
Of secondary bank (16 Kbytes)
Parameter
Parameter
,
T
A
= 2 5°C.
Flash memory endurance
Per word
Doc ID 13495 Rev 6
Test conditions
Half word (16 bits)
Test conditions
Typ
1300
1060
100K
500
500
120
Min
2.5
7.5
32
16
15
20
8
(1)
Typ after 100K
W/E cycles
Electrical characteristics
Value
Typ
Value
1400
1140
600
520
130
36
18
20
10
3
9
(1)
Max
1800
1380
Max
850
640
160
46
23
22
11
11
4
cycles
years
Unit
71/102
Unit
ms
ms
ms
ms
ms
µs
s
s
s
s
s

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