STR750FV2 STMicroelectronics, STR750FV2 Datasheet - Page 48

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STR750FV2

Manufacturer Part Number
STR750FV2
Description
ARM7TDMI-S™ 32-BIT MCU with Flash, SMI, 3 std 16-bit timers, PWM timer, fast 10-bit ADC, I2C, UART, SSP, USB and CAN
Manufacturer
STMicroelectronics
Datasheet

Specifications of STR750FV2

Smart Low Power Modes
SLOW, WFI, STOP and STANDBY with backup registers
Conversion Time
min. 3.75 μs

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Electrical parameters
48/84
Figure 23. Self-referred jitter (single and long term)
Figure 24. Cycle-to-cycle jitter
difference between N+1 consecutive clock rising edges and T
difference between N+1 consecutive clock rising edges.
N should be kept sufficiently large to have a long term jitter (ex: thousands).
For N=1, this becomes the single period jitter.
See
Cycle-to-cycle jitter (N period jitter)
This corresponds to the time variation between adjacent cycles over a random sample
of adjacent clock cycles pairs. Jitter(cycle-to-cycle) = Max(Tcycle n- Tcycle n-1) for n=1
to N.
See
Figure 23
Figure 24
CK_PLL
ACTUAL
CK_PLL
IDEAL
CK_PLL
CK_PLL
ACTUAL
IDEAL
trigger point
n
n
T
T
Tcycle 1
single period
jitter
n+1
n+1
STR750Fxx STR751Fxx STR752Fxx STR755Fxx
Tcycle 2
n+2
---
---
long term
jitter
min
Tcycle N-1
n+N
is the minimum time
n+N

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