STR912FAZ44 STMicroelectronics, STR912FAZ44 Datasheet - Page 28

• Manufacturer Part Number: STR912FAZ44
• Description: 32-bit MCU
• Manufacturer: STMicroelectronics

Specifications of STR912FAZ44

• Arm966e-s Risc Core: Harvard architecture, 5-stage pipeline, Tightly-Coupled Memories (SRAM and Flash)

Functional overview
3.15.1
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TAPs are daisy-chained, only one TAP will converse on the JTAG bus at any given time while
the other two TAPs are in BYPASS mode. The TAP positioning order within this JTAG chain
is the boundary scan TAP first, followed by the ARM debug TAP, followed by the Flash TAP.
All three TAP controllers are reset simultaneously by one of two methods:
●
●
This means that chip-level system resets from watchdog time-out or the assertion of
RESET_INn pin do not affect the operation of any JTAG TAP controller. Only global resets
effect the TAPs.
Figure 3.
In-system-programming
The JTAG interface is used to program or erase all memory areas of the STR91xFA device.
The pin RESET_INn must be asserted during ISP to prevent the CPU from fetching invalid
instructions while the Flash memories are being programmed.
Note that the 32 bytes of OTP memory locations cannot be erased by any means once
programmed by JTAG ISP or the CPU.
JTRSTn
JRTCK
JTDO
JTMS
JTCK
JTDI
A chip-level global reset, caused only by a Power-On-Reset (POR) or a Low Voltage
Detect (LVD).
A reset command issued by the external JTAG test equipment. This can be the
assertion of the JTAG JTRSTn input pin on the STR91xFA or a JTAG reset command
shifted into the STR91xFA serially.
JTAG chaining inside the STR91xFA
TDO
MAIN FLASH
TDI
JTAG TAP CONTROLLER #1
JTAG TAP CONTROLLER #3
TMS
TMS
BOUNDARY SCAN
Doc ID 13495 Rev 6
TCK
TCK
SECONDARY FLASH
TRST
TRST
TDO
TDI
register length
Instruction
BURST FLASH
MEMORY DIE
is 8 bits
TDI
JTAG
JTAG TAP CONTROLLER #2
TRST
CPU DEBUG
TCK
TMS
TDO
ARM966ES DIE
5 bits for TAP #1
4 bits for TAP #2
register length:
Instruction
STR91xFAxxx
JTAG
STR91xx