STR912FAZ47 STMicroelectronics, STR912FAZ47 Datasheet - Page 30

• Manufacturer Part Number: STR912FAZ47
• Description: ARM966E-S™ 16/32-Bit Flash MCU with Ethernet, USB, CAN, AC motor control, 4 timers, ADC, RTC, DMA
• Manufacturer: STMicroelectronics

Specifications of STR912FAZ47

• Arm966e-s Risc Core: Harvard architecture, 5-stage pipeline, Tightly-Coupled Memories (SRAM and Flash)

Functional overview
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Embedded trace module (ARM ETM9, v. r2p2)
The ETM9 interface provides greater visibility of instruction and data flow happening inside
the CPU core by streaming compressed data at a very high rate from the STR91xFA though
a small number of ETM9 pins to an external Trace Port Analyzer (TPA) device. The TPA is
connected to a host computer using USB, Ethernet, or other high-speed channel. Real-time
instruction flow and data activity can be recorded and later formatted and displayed on the
host computer running debugger software, and this software is typically integrated with the
debug software used for EmbeddedICE-RT functions such as single-step, breakpoints, etc.
Tracing may be triggered and filtered by many sources, such as instruction address
comparators, data watchpoints, context ID comparators, and counters. State sequencing of
up to three triggers is also provided. TPA hardware is commercially available and operates
with debugging software tools.
The ETM9 interface is nine pins total, four of which are data lines, and all pins can be used
for GPIO after tracing is no longer needed. The ETM9 interface is used in conjunction with
the JTAG interface for trace configuration. When tracing begins, the ETM9 engine
compresses the data by various means before broadcasting data at high speed to the TPA
over the four data lines. The most common ETM9 compression technique is to only output
address information when the CPU branches to a location that cannot be inferred from the
source code. This means the host computer must have a static image of the code being
executed for decompressing the ETM9 data. Because of this, self-modified code cannot be
traced.
Ethernet MAC interface with DMA
STR91xFA devices in 128-pin and 144-ball packages provide an IEEE-802.3-2002
compliant Media Access Controller (MAC) for Ethernet LAN communications through an
industry standard Medium Independent Interface (MII). The STR91xFA requires an external
Ethernet physical interface device (PHY) to connect to the physical LAN bus (twisted-pair,
fiber, etc.). The PHY is connected to the STR91xFA MII port using as many as 18 signals
(see pins which have signal names MII_* in
The MAC corresponds to the OSI Data Link layer and the PHY corresponds to the OSI
Physical layer. The STR91xFA MAC is responsible for:
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Data encapsulation, including frame assembly before transmission, and frame
parsing/error detection during and after reception.
Media access control, including initiation of frame transmission and recover from
transmission failure.
Doc ID 13495 Rev 6
Table
8).
STR91xFAxxx