STR912FAZ47 STMicroelectronics, STR912FAZ47 Datasheet - Page 54

• Manufacturer Part Number: STR912FAZ47
• Description: ARM966E-S™ 16/32-Bit Flash MCU with Ethernet, USB, CAN, AC motor control, 4 timers, ADC, RTC, DMA
• Manufacturer: STMicroelectronics

Specifications of STR912FAZ47

• Arm966e-s Risc Core: Harvard architecture, 5-stage pipeline, Tightly-Coupled Memories (SRAM and Flash)

Memory mapping
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Memory mapping
The ARM966E-S CPU addresses a single linear address space of 4 giga-bytes (2
address 0x0000.0000 to 0xFFFF.FFFF as shown in
from address 0x0000.0000, which is chip-select zero at address zero in the Flash Memory
Interface (FMI).
The Instruction TCM and Data TCM enable high-speed CPU operation without incurring any
performance or power penalties associated with accessing the system buses (AHB and
APB). I-TCM and D-TCM address ranges are shown at the bottom of the memory map in
Figure
Buffered and non-buffered writes
The CPU makes use of write buffers on the AHB and the D-TCM to decouple the CPU from
any wait states associated with a write operation. The user may choose to use write with
buffers on the AHB by setting bit 3 in control register CP15 and selecting the appropriate
AHB address range when writing. By default at reset, buffered writes are disabled (bit 3 of
CP15 is clear) and all AHB writes are non-buffered until enabled.
addressable items on the AHB are aliased at two address ranges, one for buffered writes
and another for non-buffered writes. A buffered write will allow the CPU to continue program
execution while the write-back is performed through a FIFO to the final destination on the
AHB. If the FIFO is full, the CPU is stalled until FIFO space is available. A non-buffered write
will impose an immediate delay to the CPU, but results in a direct write to the final AHB
destination, ensuring data coherency. Read operations from AHB locations are always direct
and never buffered.
System (AHB) and peripheral (APB) buses
The CPU will access SRAM, higher-speed peripherals (USB, Ethernet, Programmable
DMA), and the external bus (EMI) on the AHB at their respective base addresses indicated
in
separate AHB-to-APB bridge units (APB0 and APB1). These bridge units are essentially
address windows connecting the AHB to the APB. To access an individual APB peripheral,
the CPU will place an address on the AHB bus equal to the base address of the appropriate
bridge unit APB0 or APB1, plus the offset of the particular peripheral, plus the offset of the
individual data location within the peripheral.
units APB0 and APB1, and also the base address of each APB peripheral. Please consult
the STR91xFA Reference manual for the address of data locations within each individual
peripheral.
Figure
9.
9. Lower-speed peripherals reside on the APB and are accessed using two
Doc ID 13495 Rev 6
Figure 9
Figure
shows the base addresses of bridge
9. Upon reset the CPU boots
Figure 9
shows that most
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