DS17287 Maxim, DS17287 Datasheet - Page 12
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DS17287
Manufacturer Part Number
DS17287
Description
The DS17285, DS17485, DS17885, DS17287, DS17487, and DS17887 real-time clocks (RTCs) are designed to be successors to the industry-standard DS12885 and DS12887
Manufacturer
Maxim
Datasheet
1.DS17285.pdf
(31 pages)
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The RTC function continues to operate, and all the
RAM, time, calendar, and alarm memory locations
remain nonvolatile regardless of the level of the V
input. V
and maximum limits when V
V
putting the part into a low-power mode. When V
applied and exceeds V
device becomes accessible after t
is running and the oscillator countdown chain is not in
reset (Register A). This time period allows the system to
stabilize after power is applied. If the oscillator is not
enabled, the oscillator enable bit is enabled on power-
up, and the device becomes immediately accessible.
The power control function is provided by a precise,
temperature-compensated voltage reference and a
comparator circuit that monitors the V
device is fully accessible and data can be written and
read when V
V
access. If V
switched from V
when V
higher of V
from V
drops below the higher backup source. The registers
are maintained from the V
V
above V
Real-Time Clocks
Table 2. Power Control
12
CC
CC
CC
SUPPLY CONDITION
V
V
V
V
CC
CC
CC
CC
(V
(V
(V
(V
falls below V
is returned to nominal levels. After V
falls below V
____________________________________________________________________
BAT
BAT
BAT
BAT
CC
< V
< V
> V
> V
CC
BAT
PF
| V
| V
| V
| V
, read and write access is allowed after t
PF
PF
PF
PF
to the higher of V
BAT
drops below V
or V
PF
, V
BAUX
, V
BAUX
, V
BAUX
, V
BAUX
CC
CC
CC
CC
CC
or V
is less than V
BAUX
)
)
)
)
is greater than V
CC
<
>
<
>
PF
Power-Down/Power-Up
PF
BAUX
, the device inhibits read and write
to the higher of V
, the device inhibits all access,
must remain within the minimum
READ/WRITE
, the device power is switched
PF
ACCESS
PF
BAT
(power-fail trip point), the
. If V
Yes
Yes
No
No
BAT
BAT
CC
Considerations
Power Control
or V
, the device power is
is not applied. When
PF
or V
REC
PF
is greater than the
BAUX
. However, when
BAUX
, if the oscillator
POWERED BY
BAT
V
CC
BAT
source until
CC
when V
level. The
V
V
V
or V
or V
CC
CC
CC
returns
BAUX
CC
BAUX
REC
CC
CC
is
.
The time and calendar information is obtained by read-
ing the appropriate register bytes. The time, calendar,
and alarm are set or initialized by writing the appropri-
ate register bytes. The contents of the 12 time, calen-
dar, and alarm bytes can be either binary or
binary-coded decimal (BCD) format. Tables 3A and 3B
show the BCD and binary formats of the 12 time, date,
and alarm registers, control registers A to D, plus the
two extended registers that reside in bank 1 only (bank
0 and bank 1 switching is explained later in this text).
The day-of-week register increments at midnight, incre-
menting from 1 through 7. The day-of-week register is
used by the daylight saving function, and so the value
1 is defined as Sunday. The date at the end of the
month is automatically adjusted for months with fewer
than 31 days, including correction for leap years.
Before writing the internal time, calendar, and alarm
registers, the SET bit in Register B should be written to
logic 1 to prevent updates from occurring while access
is being attempted. In addition to writing the 12 time,
calendar, and alarm registers in a selected format
(binary or BCD), the data mode bit (DM) of Register B
must be set to the appropriate logic level. All 12 time,
calendar, and alarm bytes must use the same data
mode. The set bit in Register B should be cleared after
the data mode bit has been written to allow the real
time clock to update the time and calendar bytes. Once
initialized, the real time clock makes all updates in the
selected mode. The data mode cannot be changed
without reinitializing the 12 data bytes. Tables 3A and
3B show the BCD and binary formats of the 12 time,
calendar, and alarm locations.
The 24-12 bit cannot be changed without reinitializing
the hour locations. When the 12-hour format is selected,
the high order bit of the hours byte represents PM when
it is logic 1. The time, calendar, and alarm bytes are
always accessible because they are double-buffered.
Once per second, the eight bytes are advanced by one
second and checked for an alarm condition.
If a read of the time and calendar data occurs during
an update, a problem exists where seconds, minutes,
hours, etc., may not correlate. The probability of read-
ing incorrect time and calendar data is low. Several
methods of avoiding any possible incorrect time and
calendar reads are covered later in this text.
Time, Calendar, and Alarm
Locations