DS17287 Maxim, DS17287 Datasheet - Page 19

• Manufacturer Part Number: DS17287
• Description: The DS17285, DS17485, DS17885, DS17287, DS17487, and DS17887 real-time clocks (RTCs) are designed to be successors to the industry-standard DS12885 and DS12887
• Manufacturer: Maxim

The periodic interrupt causes the IRQ pin to go to an
active state from once every 500ms to once every
122µs. This function is separate from the alarm inter-
rupt, which can be output from once per second to
once per day. The periodic interrupt rate is selected
using the same Register A bits that select the square-
wave frequency (see Table 4). Changing the Register A
bits affects both the square-wave frequency and the
periodic interrupt output. However, each function has a
separate enable bit in Register B. The SQWE and E32k
bits control the square-wave output. Similarly, the peri-
odic interrupt is enabled by the PIE bit in Register B.
The periodic interrupt can be used with software coun-
ters to measure inputs, create output intervals, or await
the next needed software function.
The DS17x85 executes an update cycle once per sec-
ond regardless of the SET bit in Register B. When the
SET bit in Register B is set to 1, the user copy of the
double-buffered time, calendar, and alarm bytes is
frozen and does not update as the time increments.
However, the time countdown chain continues to
update the internal copy of the buffer. This feature
allows time to maintain accuracy independent of read-
ing or writing the time, calendar, and alarm buffers, and
also guarantees that time and calendar information is
consistent. The update cycle also compares each
alarm byte with the corresponding time byte and issues
Figure 4. UIP and Periodic Interrupt Timing
UIP
Periodic Interrupt Selection
UF
PF
t
BUC
= DELAY TIME BEFORE UPDATE CYCLE = 244μs.
Update Cycle
____________________________________________________________________
t
BUC
t PI
1 SECOND
an alarm if a match or if a don’t care code is present in
all alarm locations.
There are three methods that can handle access of the
RTC that avoid any possibility of accessing inconsistent
time and calendar data. The first method uses the
update-ended interrupt. If enabled, an interrupt occurs
after every update cycle that indicates that over 999ms
are available to read valid time and date information. If
this interrupt is used, the IRQF bit in Register C should
be cleared before leaving the interrupt routine.
A second method uses the update-in-progress (UIP) bit
in Register A to determine if the update cycle is in
progress. The UIP bit pulses once per second. After
the UIP bit goes high, the update transfer occurs 244µs
later. If a low is read on the UIP bit, the user has at least
244µs before the time/calendar data is changed.
Therefore, the user should avoid interrupt service rou-
tines that would cause the time needed to read valid
time/calendar data to exceed 244µs.
The third method uses a periodic interrupt to determine
if an update cycle is in progress. The UIP bit in Register
A is set high between the setting of the PF bit in
Register C (see Figure 4). Periodic interrupts that occur
at a rate of greater than t
information to be reached at each occurrence of the
periodic interrupt. The reads should be complete within
1 (t
the update cycle.
PI/2
+ t
BUC
t
PI/2
Real-Time Clocks
) to ensure that data is not read during
t
PI/2
BUC
allow valid time and date
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