DS4830 Maxim, DS4830 Datasheet
DS4830
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DS4830 Summary of contents
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... General Description The DS4830 provides a complete optical control, cali- bration, and monitor solution with a low-power, 16-bit, MAXQ20 microcontroller core providing generous pro- gram and RAM data memory. I/O resources include a fast/accurate analog-to-digital converter (ADC), fast comparators with an internal comparison digital-to-ana- ...
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... CONDITIONS CPU mode, all analog disabled I CPU (Notes FASTCOMP Both sample/hold I ADC I Per channel (Note 4) DACS V Monitors V (Note Monitors V (Note 1) BOH DD V (Note 1) REG18 V (Note 1) REG285 DS4830 MIN TYP MAX UNITS 3.0 3.6 0 0.3 DD 0 2.1 0.3 -0.5 +0.8 = 3.3V +25NC MIN ...
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... T = -40NC to +85NC ERR A f XCLK (Note 4mA (Note 1) OL1 -4mA (Note 1) OH1 PU1 PIN R HISt R LOSt R HIA R LOA R HIB R LOB DS4830 = 3.3V +25NC MIN TYP MAX UNITS 20 MHz 10 ±5.5 20 133 MHz -0.3 0 27.6 8 25 ...
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... DAC-SINK t DAC SYMBOL CONDITIONS I FASTCOMP V FS-COMP Differential mode, 2.2nF capacitor INL at input Differential mode, 2.2nF capacitor DNL at input V OFFSET-COMP R (Note 6) IN-COMP C IN-COMP f COMP DS4830 = 3.3V +25NC MIN TYP MAX UNITS 12 Bits -1.25 +1. 2.5 V See the DC Electrical Characteristics 12 LSB 1 LSB ...
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... ADC Offset V GP[15:0] Input Resistance ADC Sample Rate ADC Temperature Conversion Time Internal Temperature Measurement Error Remote Temperature Measurement Error (DS4830 Error Only) SAMPLE/HOLDDCELECTRICALCHARACTERISTICS (V = 3.0V to 3.6V -40NC to +85NC, unless otherwise noted. Typical values are PARAMETER Sample/Hold Input Range Sample/Hold Capacitance ...
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... BUF t (Note 10) HD:STA t LOW t HIGH t SU:STA Receive t HD:DAT Transmit t (Notes 11, 12) SU:DAT C (Note 13 (Note 13 (Note 13 SU:STO t (Note 14 BIN DS4830 = 3.3V +25NC MIN TYP MAX -40 +85 20,000 100 1.) MIN TYP MAX 400 100 1.3 0.6 1.3 0.6 0.6 0 300 ...
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... MIN TYP t /2 MSPICK - t SPI_RF t /2 MSPICK - t SPI_RF t /2 MSPICK - t SPI_RF 2t SPI_RF MSPICK - t SPI_RF t /2 SCL t SPI_RF t SPI_RF t SPI_RF DS4830 MAX UNITS kHz % MAX UNITS f /2 MHz SYS f /4 MHz SYS ...
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... SYMBOL CONDITIONS V REF TLQ t DVTH t THDX Figure 3 and Figure 4.) MIN TYP t + SSPICK t SPI_RF t SPI_RF 5) MIN TYP 0.5 0.5 0.25 0. the SCL signal. LOW IH:MIN DS4830 MAX UNITS SSPICK + ns 2t SPI_RF MAX UNITS 0.125 the SCL signal) to ...
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... HIGH t t HD:DAT SU:DAT REPEATED START R R DS4830 Timing Diagrams HD:STA t SU:STA SU:STO ...
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... MCH MCL t MOH t MOV MSB MSB MIS MIH MSB MSB-1 SAMPLE SHIFT SAMPLE t SSPICK t t SCH SCL t t SIS SIH MSB MSB-1 t SOV MSB MSB-1 DS4830 Timing Diagrams (continued) 1/0 0/1 1/1 0/0 t SPI_RF t MLH LSB LSB t SSH t SD 1/0 0/1 1/1 0/0 LSB t SPI_RF t SLH LSB ...
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... Integrated Products Optical Microcontroller V REF DVTH THDX DS4830 Timing Diagrams (continued TLQ ...
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... Open Drain Impedance High Open Drain Impedance High Open Drain Impedance Push-Pull, 55µA Pullup Extra Strong None 2.85V Push-Pull, 55µA Pullup Extra Strong None V DD High None Impedance DS4830 Pin Configuration 21 20 GP13 19 GP12 18 GP11 17 GP10 16 REG18 15 GP9 14 GP8 13 GP7 12 GP6 11 GP5 ...
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... Push-Pull 55µA Pullup ADC-S15 Push-Pull 55µA Pullup SHEN0 3-Wire Data Push-Pull 55µA Pullup MDIO Push-Pull, 55µA Pullup Strong 3-Wire Clock Push-Pull 55µA Pullup MCL DS4830 SELECTABLEFUNCTIONS ADC- ADC- — SHN0 D1N ADC- ADC-S4 — D2P ADC- ADC-S5 — D2N ADC- SPI ...
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... Internal Reference DAC5 REFINB Push-Pull 55µA Pullup or Internal Reference DAC6, FS Push-Pull, = REFINB 55µA Pullup Strong or Internal Reference ADC- Push-Pull 55µA Pullup REFINB DS4830 SELECTABLEFUNCTIONS SPI — PW7 MSPICS — — — — — — — — — — — — PW0 — ...
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... C Slave Clock), SDA ( slave interface is disabled. Pin Description (continued) SELECTABLEFUNCTIONS (FIRSTCOLUMNISDEFAULTFUNCTION) DAC7 REFINB PW7 — or Internal Reference — — — Selectable Functions DESCRIPTION 2 C Master Data Slave Data). These also function as a DS4830 PORT — P2.7 — — ...
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... USER 03FFh PROGRAM MEMORY SRAM 0000h 0000h MEMORY MANAGEMENT UNIT (MMU) DATA POINTERS DP[0], DP[1 (BP+OFFS) DPC MAXQ20 CORE SYSTEM INSTRUCTION MODULES/REGISTERS DECODE (src, dst TRANSPORT DETERMINATION) 12-BIT D-PWM x 10 DAC x 8 20MHz OSC CORE /2 CLOCK DS4830 DATA V REF 2.5V ±1% ...
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... Figure 6 shows the DS4830’s memory map when executing from program memory space. Refer to the DS4830 User’s Guide for memory map information when executing from data or ROM space. The incorporation of flash memory allows field upgrade of the firmware. Flash memory can be password protected with a 16-word key, denying access to program memory by unauthorized individuals ...
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... Routines within the utility ROM are firmware-accessible and can be called as subroutines by the application software. More information on the utility ROM contents is contained in the DS4830 User’s Guide. Some applications require protection against unau- thorized viewing of program code memory. For these ...
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... SP. The RET, RETI, POP, and POPI opera- tions retrieve the value at SP and then decrement SP. The microcontroller’s flash memory can be programmed by one of two methods: in-system programming or in- application programming. These provide great flexibility in DS4830 RESET INITIATED BY 2 POR SELF-RESET, OR RST PIN. ...
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... The peripheral registers define addi- tional functionality, and the functionality is broken up into discrete modules. Both the system registers and the peripheral registers are described in detail in the DS4830 User’s Guide. The device generates its 10MHz instruction clock (MOSC) internally using a ring oscillator. On power-up, the oscil- lator’ ...
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... SFRs for each of the general-purpose timers. The timer and counter SFRs are accessed in module 0 and module 3. Detailed information regarding the timer/coun- ter block can be found in theDS4830 User’s Guide. The hardware multiplier (multiply-accumulate, or MAC module very powerful tool, especially for applica- tions that require heavy calculations ...
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... Each DAC can be individually disabled and put into a low-power power-down mode using DACCFG. An external reset does not affect the DAC outputs DAC output is used during the lifetime of the DS4830, the DAC must always be enabled to guarantee meeting the INL and offset specifications pin is used for a DAC, it should be used only for the DAC function. The pin’ ...
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... ADC-TEXT_B(+/-) tor, charge injection nulling switches, and a buffer. ADC-TINT Also included is a discharge circuit used to discharge parasitic capacitance on the input node and the sample capacitor before sampling begins. The negative input pins can be used to reduce ground offsets and noise. DS4830 Sample/Hold ...
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... Integrated Products Optical Microcontroller The quick-trip-related SFRs are accessed in module 5. Refer to the quick trip section of the DS4830 User’s Guide for more information. 2 ...
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... The SPI master-related SFRs are accessed in module 5. The SPI slave-related SFRs are accessed in module 1. Details can be found in the SPI section of the DS4830 User’s Guide. 3-Wire Interface Module The DS4830 controls devices like the MAX3798/MAX3799 over a proprietary 3-wire interface ...
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... Integrated Products Optical Microcontroller To achieve the best results when using the DS4830, decouple the V tor ...
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... TQFN-EP* “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE 40 TQFN-EP DS4830 Package Information PACKAGE OUTLINE LAND CODE NO. ...
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... MAX3948 SCL TOUTC SDA VOUT CSEL VCCT VSEL TOUTA R3 MAX3948 SCL TOUTC SDA VOUT CSEL VCCT VSEL TOUTA MAX3948 SCL TOUTC SDA VOUT CSEL DS4830 MODE_DEF2 (SDA) SLAVE DS4830 MODE_DEF1 (SCL) SCL SDA CSEL 13-BIT ADC BIAS RSSI MONITOR MONITOR ...
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... Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 2011 Maxim Integrated Products © Optical Microcontroller DESCRIPTION Maxim is a registered trademark of Maxim Integrated Products, Inc. DS4830 Revision History PAGES CHANGED — ...