DS4830 Maxim, DS4830 Datasheet - Page 24

• Manufacturer Part Number: DS4830
• Description: The DS4830 provides a complete optical control, calibration, and monitor solution with a low-power, 16-bit, MAXQ20 microcontroller core providing generous program and RAM data memory
• Manufacturer: Maxim

The device provides an internal temperature sensor for
die temperature monitoring and two external remote
temperature-sensing channels. In external temperature
mode, current is forced into an external diode that is con-
nected between user-specified channel pins. The diode
temperature is obtained by measuring the diode voltages
at multiple bias currents.
These temperature channels can be enabled independ-
ently by setting the appropriate bit locations in the
TEMPCN register. Whenever a temperature conversion
is complete, the corresponding flag (INTDAI for internal
conversion, EX0DAI and EX1DAI for external conversion)
is set. These can be configured to cause an interrupt,
and can be cleared by software. The temperature meas-
urement resolution is 0.0625NC.
The device can use all the three modes explained above
simultaneously by using a time-slicing mechanism per-
formed by the internal controller. The ADC-related SFRs
are accessed in module 1 and module 2. For details
about this and the three blocks, refer to the ADC section
of the DS4830 User’s Guide.
The device supports 10-bit quick-trip comparison func-
tionality. The quick trips are required to continuously
monitor 5 to 14 channels in a round-robin sequence.
The quick- trip controller allows the user control of the list
of channels to monitor. Each mode has a corresponding
choice of list of channels for the round robin.
In any mode of quick-trip operation, the quick trip (ana-
log) performs two comparisons on any selected channel.
1) Comparison with a high-threshold value.
2) Comparison with a low-threshold value.
Any comparison above the high-threshold value or below
the low-threshold value causes a bit to set in the cor-
responding register. This bit can be used to trigger an
interrupt. The threshold values are stored in 32 internal
register (16 for low-threshold settings and 16 for high-
threshold settings). The quick-trip controller provides the
appropriate sequence of clock and threshold values for
the quick trips. Because the quick trips and the ADC use
the same input pins, the controller ensures that no colli-
sion takes place.
SMBus is a trademark of Intel Corp.
Fast Comparator/Quick Trips
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Temperature Measurement
The quick-trip-related SFRs are accessed in module
5. Refer to the quick trip section of the DS4830 User’s
Guide for more information.
The device provides two independent I
interfaces: one is a master and the other is a slave.
The device features an internal I
interface for communication with a wide variety of exter-
nal I
bidirectional bus using two bus lines: the serial-data line
(MSDA) and the serial-clock line (MSCL). For the I
compatible master, the device has ownership of the I
bus and drives the clock and generates the START and
STOP signals. This allows the device to send data to a
slave or receive data from a slave.
When the I
MSDA and MSCL can be used as GPIO pins P1.0 and
P1.1, respectively, and accessed through PO1/PI1/PD1.
The device also features an internal I
interface for communication with a host. Furthermore,
the device can be in-system programmed (bootloaded)
through the I
face signals used by the I
SDA. For the I
relies on an externally generated clock to drive SCL and
responds to data and commands only when requested
by the I
face is open drain and requires external pullup resistors.
Both the I
work in SMBusK-compatible mode for communication
with other SMBus devices. To achieve this, a 30ms timer
has been implemented on the I
face to make the interface SMBus compatible. The pur-
pose of this timer is to issue a timeout interrupt and thus
the firmware can reset the I
when the SCL is held low for longer than 30ms. The timer
only starts when none of the following conditions is true:
1) The I
2) The I
I
Optical Microcontroller
and there is no communications on the bus.
SMBus-compatible mode.
2
2
C-Compatible Interface Modules
C devices. The I
2
2
C master device. The I
2
C-compatible slave interface is in the idle state
C-compatible slave interface is not working in
2
C-compatible master and slave interfaces can
2
2
C-compatible master interface is disabled,
C-compatible slave interface. The two inter-
2
I
C-compatible slave interface, the device
2
I
C-Compatible Master Interface
2
C-Compatible Slave Interface
2
C-compatible master bus is a
2
C slave interface are SCL and
2
C-compatible slave interface
2
2
C-compatible slave inter-
C-compatible slave inter-
2
C-compatible master
2
SMBus Timeout
C-compatible slave
DS4830
2
C-compatible
The two inter-
2
2
C-
C