71M6543G Maxim, 71M6543G Datasheet - Page 44

• Manufacturer Part Number: 71M6543G
• Description: The 71M6543F/71M6543H are Teridian's 4th-generation polyphase metering system-on-chips (SoCs) with a 5MHz, 8051-compatible MPU core, low-power real-time clock (RTC) with digital temperature compensation, flash memory, and LCD driver
• Manufacturer: Maxim

71M6543F/H and 71M6543G/GH Data Sheet
IP1(SFR 0xB9)
polling sequence as shown in
44
Register
IP0
IP1
Changing interrupt priorities while interrupts are enabled can easily cause software defects. It is best
to set the interrupt priority registers only once during initialization before interrupts are enabled.
SFR 0xA9
SFR 0xB9
(Table
Address
36). If requests of the same priority level are received simultaneously, an internal
Table 36: Interrupt Priority Registers (IP0 and IP1)
© 2008–2011 Teridian Semiconductor Corporation
(MSB)
Bit 7
Table 37
–
–
IP1[x]
0
0
1
1
Table 35: Interrupt Priority Levels
Bit 6
determines which request is serviced first.
–
–
IP0[x]
0
1
0
1
IP0[5]
IP1[5]
Bit 5
Level 0 (lowest)
Level 1
Level 2
Level 3 (highest)
IP0[4]
IP1[4]
Bit 4
Priority Level
IP0[3]
IP1[3]
Bit 3
IP0[2]
IP1[2]
Bit 2
IP0[1]
IP1[1]
Bit 1
IP0[0]
IP1[0]
(LSB)
Bit 0
v1.2