73S1209F Maxim, 73S1209F Datasheet
73S1209F
Related parts for 73S1209F
73S1209F Summary of contents
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... Teridian 73S8010R/C ICs. This makes the solution immediately able to support multi-card slots or multi-SAM architectures. In addition, the 73S1209F features a 5x6 PINpad interface, 9 user I/Os, 2 LED outputs (programmable current), multiple interrupt options and an analog voltage input (for DC voltage monitoring such as battery level detection) that make it suitable for low-cost PINpad reader devices ...
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FEATURES 80515 Core: • 1 clock cycle per instruction (most instructions) • CPU clocked up to 24MHz • 32kB Flash memory with security • 2kB XRAM (User Data Memory) • 256 byte IRAM • Hardware watchdog timer Oscillators: • Single ...
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... Packaging Information .............................................................................................................. 119 5 Ordering Information ...................................................................................................................... 121 6 Related Documentation .................................................................................................................. 121 7 Contact Information ........................................................................................................................ 121 Revision History ...................................................................................................................................... 122 Rev. 1.2 Table of Contents 73S1209F Data Sheet ...
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... Figure 22: Creation of Synchronous Clock Start/Stop Mode Stop Bit in Sync Mode ................................. 77 Figure 23: Operation of 9-bit Mode in Sync Mode ...................................................................................... 78 Figure 24: 73S1209F Typical PINpad, Smart Card Reader Application Schematic ................................. 103 Figure 25: 73S1209F Typical SIM / Smart Card Reader Application Schematic ..................................... 104 Figure 26: 12 MHz Oscillator Circuit ......................................................................................................... 110 Figure 27: Digital I/O Circuit ...................................................................................................................... 110 Figure 28: Digital Output Circuit ...
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... DS_1209F_004 Tables Table 1: 73S1209F Pinout Description ......................................................................................................... 8 Table 2: MPU Data Memory Map ................................................................................................................ 11 Table 3: Flash Special Function Registers ................................................................................................. 13 Table 4: Internal Data Memory Map ........................................................................................................... 14 Table 5: Security Control Registers ............................................................................................................ 17 Table 6: IRAM Special Function Registers Locations ................................................................................. 18 Table 7: IRAM Special Function Registers Reset Values ........................................................................... 19 Table 8: XRAM Special Function Registers Reset Values ......................................................................... 21 Table 9: PSW Register Flags ...
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Table 57: The LEDCtl Register ................................................................................................................... 53 Table 58: The DAR Register ....................................................................................................................... 57 Table 59: The WDR Register ...................................................................................................................... 57 Table 60: The SWDR Register.................................................................................................................... 58 Table 61: The RDR Register ....................................................................................................................... 58 Table 62: The SRDR Register .................................................................................................................... ...
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... FLASH CORE IRAM INTERFACE 256B ALU WATCH- PMU DOG DATA TIMER XRAM PORTS 2KB ISR SERIAL PERIPHERAL INTERFACE and SFR LOGIC 73S1209F Data Sheet VCC VCC CONTROL LOGIC GND RST CLK SMART CARD I/O ISO INTERFACE AUX1 AUX2 PRES PRESB EXTERNAL SCLK ...
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... I TXD INT3 Table 1: 73S1209F Pinout Description Description Figure 26 MPU clock crystal oscillator input pin. A 1MΩ resistor is required between pins X12IN and X12OUT. Figure 26 MPU clock crystal oscillator output pin. Figure 32 Keypad row input sense. Figure 33 Keypad column output scan pins. ...
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... Figure 36 Analog input pin. This signal goes to a programmable comparator and is used to sense the value of an external voltage. Figure 35 Input pin for use in programming security fuse. It should be connected to ground when not in use. Figure 35 Test pin, should be connected to ground. 73S1209F Data Sheet 9 ...
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Pin Name VDD N GND 9 7 GND RESET See the figures in the Equivalent ...
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... Included on chip are an 8051-compatible microprocessor (MPU) which executes up to one instruction per clock cycle (80515), a fully integrated IS0-7816 compliant smart card interface, expansion smart card interface, serial interface, I2C interface keypad interface, 2 LED drivers, RAM, FLASH memory, and a variety of I/O pins. A functional block diagram of the 73S1209F is shown in Figure 1. ...
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... Flash and XRAM writes. Before setting FLSH_PWE, all interrupts need to be disabled by setting EAL = 1. Table 3 shows the location and description of the 73S1209F flash-specific SFRs. Any flash modifications must set the CPUCLK to operate at 3.6923 MHz before any flash memory operations are executed to insure the proper timing when modifying the flash memory ...
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... Must be re-written for each new Mass Erase cycle. R/W Bit 6 (SECURE): Enables security provisions that prevent external reading of flash memory and CE program RAM. This bit is reset on chip reset and may only be set. Attempts to write zero are ignored. Rev. 1.2 73S1209F Data Sheet Must be proceeded by a write to 13 ...
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Internal Data Memory: The Internal data memory provides 256 bytes (0x00 to 0xFF) of data memory. The internal data memory address is always one byte wide and can be accessed by either direct or indirect addressing. The Special Function Registers ...
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... XRAM 0x1F 0x18 0x17 0x10 0x0F 0x08 0x07 0x00 Figure 2: Memory Map 73S1209F Data Sheet Use Indirect Direct Access Access Byte RAM SFRs Byte RAM Bit/Byte RAM Register bank 3 Register bank 2 Register bank 1 Register bank 0 Internal Data Memory ...
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Program Security Two levels of program and data security are available. Each level requires a specific fuse to be blown in order to enable or set the specific security mode. Mode 0 security is enabled by setting the SECURE ...
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... Indicates the state of the SEC pin. The SEC pin is held low by a pull-down resistor. The user can force this pin high during boot sequence time to indicate to the firmware that sec mode 1 is desired. R/W Bit 1 (SECSET1): See Program Security section. R/W Bit 0 (SECSET0): See Program Security section. Rev. 1.2 Table 5: Security Control Registers 73S1209F Data Sheet 17 ...
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... SP Only a few addresses are used, the others are not implemented. SFRs specific to the 73S1209F are shown in bold print (gray background). Any read access to unimplemented addresses will return undefined data, while most write access will have no effect. However, a few locations are reserved and not user configurable in the 73S1209F ...
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... Interrupt Priority Register 0 Serial Port 0, Reload Register, low byte Flash Control Flash Page Address Interrupt Enable Register 1 Interrupt Priority Register 1 Serial Port 0, Reload Register, high byte Serial Port 1, Reload Register, high byte Interrupt Request Control Register Timer 2 Control 73S1209F Data Sheet 19 ...
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Name Location Reset Value PSW 0xD0 0x00 KCOL 0XD1 0x1F KROW 0XD2 0x3F KSCAN 0XD3 0x00 KSTAT 0XD4 0x00 KSIZE 0XD5 0x00 KORDERL 0XD6 0x00 KORDERH 0XD7 0x00 BRCON 0xD8 0x00 A 0xE0 0x00 B 0xF0 0x00 20 Description Program ...
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... External Interrupt Control 3 External Interrupt Control 4 External Interrupt Control 5 External Interrupt Control 6 MPU Clock Control Analog Compare Register TRIM Pulse Control FUSE Control VDDFault Control Security Register Miscellaneous Control Register 0 Miscellaneous Control Register 1 LED Control Register 73S1209F Data Sheet ...
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Program Status Word (PSW): MSB CV AC Bit Symbol PSW.7 CV Carry flag. PSW.6 AC Auxiliary Carry flag for BCD operations. PSW.5 F0 General purpose Flag 0 available for user. PSW.4 RS1 Register bank select control bits. The contents of ...
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... Oscillator and Clock Generation The 73S1209F has a single oscillator circuit for the main CPU clock. The oscillator circuit is designed to operate with various crystal or external clock frequencies. An internal divider working in conjunction with a PLL and VCO provides a 96MHz internal clock within the 73S1209F. 96 MHz is the recommended frequency for proper operation of specific peripheral blocks such as the specific timers, ISO-7816 UART and interfaces and keypad ...
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MCount(2:0) HOSCen X12IN HIGH XTAL 12.00MHz OSC X12OUT CPUCKDiv See SC Clock descriptions for more accurate diagram SCCKenb Figure 3: Clock Generation and Control Circuits 24 M DIVIDER 12.00MHz /(2 MCLK 96MHz Phase VCO Freq HCLK DET CPU ...
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... The MPU clock that drives the CPU core defaults to 3.6923MHz after reset. The MPU clock is scalable by configuring the MPU Clock Control register. Rev. 1.2 = 96MHz XTAL F (MHz) Mcount (N) XTAL 12.00 2 9.60 3 8.00 4 6.86 5 6.00 6 0x0A Table 12: The MCLKCtl Register SCEN – – MCT.2 Function . The default value is MCount = 2h such that XTAL 73S1209F Data Sheet LSB MCT.1 MCT.0 25 ...
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... The CPU clock is available as an output on pin CPUCLK (68-pin version only). Note: The crystal should be placed as close as possible to the IC, and vias should be avoided. 26 0x0C Table 13: The MPUCKCtl Register MDIV.5 MDIV.4 MDIV.3 MDIV.2 MDIV.1 MDIV.0 Function 73S1209F 1MΩ 12MHz 22pF 22pF Figure 4: Oscillator Circuit LSB ...
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... INT0 and the program can resume. Figure 6 shows the detailed logic for waking up the 73S1209F from a power down state using these specific interrupt sources. Figure 7 shows the timing associated with the power down mode. ...
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USR0 USR1 USR[7:0] Control USR2 USR3 USR4 USRxINTSrc set to 4(ext INT0 high) USR5 or USR6 6(ext INT0 low) USR7 INT4 INT5 RESETB Notes: 1. The counters are clocked by the MPUCLK Terminal count (high at overflow) ...
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... Rev. 1.2 0x00 Table 14: The INT5Ctl Register – – – – Function 0x00 Table 15: The MISCtl0 Register – – – – Function PCON register to stop the CPU core. The MPU is not operative in this 73S1209F Data Sheet LSB KPIEN KPINT LSB SLPBK SSEL 29 ...
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Miscellaneous Control Register 1 (MISCtl1): 0xFFF2 MSB – – Bit Symbol MISCtl1.7 – MISCtl1.6 – Flash Read Pulse enable (low). If FRPEN=1, the Flash Read signal is passed through with no change. When FRPEN=0, a one-shot circuit that shortens the ...
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... PCON.4 – PCON.3 GF1 General purpose flag 1. PCON.2 GF0 General purpose flag 1. PCON.1 STOP Sets CPU to Stop mode. PCON.0 IDLE Sets CPU to Idle mode. Rev. 1.2 0x00 Table 18: The PCON Register – – GF1 GF0 Function 73S1209F Data Sheet LSB STOP IDLE 31 ...
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... External interrupts are the interrupts external to the 80515 core, i.e. signals that originate in other parts of the 73S1209F, for example the USR I/O, smart card interface, analog comparators, etc. The external the 73S1209F, for example the USR I/O, smart card interface, analog comparators, etc. The external interrupt configuration is shown in Figure 8. ...
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... ET1 = 0 – disable timer 1 overflow interrupt. IEN0.2 EX1 EX1 = 0 – disable external interrupt 1. IEN0.1 ET0 ET0 = 0 – disable timer 0 overflow interrupt. IEN0.0 EX0 EX0 = 0 – disable external interrupt 0. Rev. 1.2 0x00 Table 19: The IEN0 Register – ES0 ET1 EX1 Function 73S1209F Data Sheet LSB ET0 EX0 33 ...
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Interrupt Enable 1 Register (IEN1): 0xB8 MSB – SWDT Bit Symbol IEN1.7 – IEN1.6 SWDT Not used for interrupt control. IEN1.5 EX6 EX6 = 0 – disable external interrupt 6. IEN1.4 EX5 EX5 = 0 – disable external interrupt 5. ...
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... I2FR = 1 external interrupt 3 positive transition active. T2CON.4 – T2CON.3 – T2CON.2 – T2CON.1 – T2CON.0 – Rev. 1.2 0x00 Table 22: The TCON Register TF0 TR0 IE1 IT1 Function 0x00 Table 23: The T2CON Register I2FR – – – Function 73S1209F Data Sheet LSB IE0 IT0 LSB – – 35 ...
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Interrupt Request Register (IRCON): 0xC0 MSB – – Bit Symbol IRCON.7 – IRCON.6 – IRCON.5 IEX6 External interrupt 6 flag. IRCON.4 IEX5 External interrupt 5 flag. IRCON.3 IEX4 External interrupt 4 flag. IRCON.2 IEX3 External interrupt 3 flag. IRCON.1 IEX2 ...
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... Enable external interrupt 5 EX6 Enable external interrupt 6 1.7.3.4 Power Down Interrupt Logic The 73S1209F contains special interrupt logic to allow INT0 to wake up the CPU from a power down (CPU STOP) state. See the Power Control Modes 1.7.3.5 Interrupt Priority Level Structure All interrupt sources are combined in groups, as shown in Table 27. ...
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Interrupt Priority 1 Register (IP1): 0xB9 MSB – – IP1.x 1.7.3.6 Interrupt Sources and Vectors Table 32 shows the interrupts with their associated flags and vector addresses. Interrupt Request Flag Description N/A IE0 TF0 IE1 TF1 RI0/TI0 RI1/TI1 IEX2 IEX3 ...
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... UART The 80515 core of the 73S1209F includes two separate UARTs that can be programmed to communicate with a host. The 73S1209F can only connect one UART at a time since there is only one set of TX and Rx pins. The MISCtl0 register is used to select which UART is connected to the TX and RX pins. Each UART has a different set of operating modes that the user can select according to their needs ...
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Power Control Register 0 (PCON): 0x87 The SMOD bit used for the baud rate generator is set up via this register. MSB SMOD – Bit Symbol PCON.7 SMOD PCON.6 – PCON.5 – PCON.4 – PCON.3 GF1 PCON.2 GF0 PCON.1 STOP ...
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... Table 37: The MISCtl0 Register – – – – Function This bit places the 73S1209F into a power down state UART loop back testing mode. The pins TXD and RXD are to be connected together externally (with SLPBK =1) and therefore: SLPBK SSEL Mode 0 ...
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Serial Interface 0 Control Register (S0CON): 0x9B Transmit and receive data are transferred via this register. MSB SM0 SM1 Bit Symbol S0CON.7 SM0 These two bits set the UART0 mode: Mode S0CON.6 SM1 S0CON.5 SM20 Enables the inter-processor communication feature. ...
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... Transmit interrupt flag, set by hardware after completion of a serial transfer. Must be cleared by software. Receive interrupt flag, set by hardware after completion of a serial reception. Must be cleared by software. or SM21 in S1CON set to 1. When the master processor outputs 73S1209F Data Sheet LSB TI1 RI1 Baud Rate variable variable ...
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... (T0 and T1 are the timer gating inputs derived from USR[0:7] pins, see the Ports section). Since it takes 2 machine cycles to recognize a 1-to-0 event, the maximum input count rate is 1/2 of the oscillator frequency. There are no restrictions on the duty cycle, however to ensure proper recognition state, an input should be stable for at least 1 machine cycle. ...
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... Rev. 1.2 Function 13-bit Counter/Timer. 16-bit Counter/Timer. 8-bit auto-reload Counter/Timer. If Timer 1 M1 and M0 bits are set to '1', Timer 1 stops. If Timer 0 M1 and M0 bits are set to '1', Timer 0 acts as two independent 8-bit Timer/Counters. 73S1209F Data Sheet 45 ...
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... This requirement imposes an obligation on the programmer to issue two instructions. The first instruction sets WDT and the second instruction sets SWDT. The maximum delay allowed between setting WDT and SWDT is 12 clock cycles. If this period has expired and SWDT has ...
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... EX3 = 0 – disable external interrupt 3. IEN1.1 EX2 EX2 = 0 – disable external interrupt 2. IEN1.0 – Rev. 1.2 0x00 Table 44: The IEN0 Register ET2 ES0 ET1 EX1 Function 0x00 Table 45: The IEN1 Register EX6 EX5 EX4 EX3 Function 73S1209F Data Sheet LSB ET0 EX0 LSB EX2 47 ...
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Interrupt Priority 0 Register (IP0): 0xA9 MSB – WDTS Bit Symbol IP0.6 WDTS Watchdog timer status flag. Set when the watchdog timer has expired. The internal reset will be generated, but this bit will not be cleared by the reset. ...
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... User (USR) Ports The 73S1209F includes 9 pins of general purpose digital I/O (GPIO). On reset or power-up, all USR pins are inputs until they are configured for the desired direction. The pins are configured and controlled by the USR and UDIR SFRs. Each pin declared as USR can be configured independently as an input or output with the bits of the UDIRn registers ...
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External Interrupt Control Register (USRIntCtl1) : 0xFF90 MSB – U1IS.6 External Interrupt Control Register (USRIntCtl2) : 0xFF91 MSB – U3IS.6 External Interrupt Control Register (USRIntCtl3) : 0xFF92 MSB – U5IS.6 External Interrupt Control Register (USRIntCtl4) : 0xFF93 MSB – U7IS.6 ...
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... DS_1209F_004 1.7.8 Analog Voltage Comparator The 73S1209F includes a programmable comparator that is connected to the ANA_IN pin. The comparator can be configured to trigger an interrupt if the input voltage rises above or falls below a selectable threshold voltage. The comparator control register should not be modified when the analog interrupt (ANAIEN bit in the INT6Ctl generated when modifying the threshold ...
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External Interrupt Control Register (INT6Ctl): 0xFF95 MSB – – Bit Symbol INT6Ctl.7 – INT6Ctl.6 – INT6Ctl.5 VFTIEN VDD fault interrupt enable. INT6Ctl.4 VFTINT VDD fault interrupt flag. 2 INT6Ctl.3 I2CIEN I C interrupt enabled. 2 INT6Ctl.2 I2CINT I C interrupt ...
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... LED Drivers The 73S1209F provides two dedicated output pins for driving LEDs. The LED driver pins can be configured as current sources that will pull to ground to drive LEDs that are connected to VDD without the need for external current limiting resistors. These pins may be used as general purpose outputs with the programmed pull-down current and a strong (CMOS) pull-up, if enabled ...
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... I C Master Interface The 73S1209F includes a dedicated fast mode, 400kHz I or write bytes of data per data transfer frame. The MPU communicates with the interface through six dedicated SFR registers: • Device Address (DAR) • Write Data (WDR) • Secondary Write Data (SWDR) • ...
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... LSB MSB LSB 1 10-17 ACK bit 2 Figure Write Mode Operation IEN1 and IRCON registers for masking and flag operation. 73S1209F Data Sheet 18 18 ACK bit ACK bit STOP STOP condition condition Secondary Write Data [7:0] MSB LSB 18 19-26 27 ACK bit ...
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Figure 10 shows the timing of the I Transfer length (CSR bit0) Start I2C (CSR bit1) I2c_Interrupt SDA Device Address MSB SCL START condition Transfer length (CSR bit0) Start I2C (CSR bit1) I2c_Interrupt SDA Device Address MSB SCL START condition ...
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... WDR.7 WDR.6 WDR.5 WDR.4 Data to be written to the I WDR.3 WDR.2 WDR.1 WDR.0 Rev. 1.2 0x00 Table 58: The DAR Register DVADR.1 Function 0x00 Table 59: The WDR Register WDR.4 WDR.3 WDR.2 Function 2 C slave device. 73S1209F Data Sheet LSB DVADR.0 I2CRW LSB WDR.1 WDR.0 57 ...
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I2C Secondary Write Data Register (SWDR): 0XFF82 MSB SWDR.7 SWDR.6 SWDR.5 Bit SWDR.7 SWDR.6 SWDR.5 SWDR.4 Second Data byte to be written to the I and Status register (CSR) is set = 1. SWDR.3 SWDR.2 SWDR.1 SWDR.0 I2C Read Data ...
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... Table 62: The SRDR Register SRDR.4 SRDR.3 SRDR.2 Function 2 C slave device if bit 0 (I2CLEN) of the Control 0x00 Table 63: The CSR Register – – – AKERR Function 2 C transaction. Automatically reset to 0 when the bus 73S1209F Data Sheet LSB SRDR.1 SRDR.0 LSB I2CST I2CLEN 59 ...
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External Interrupt Control Register (INT6Ctl): 0xFF95 MSB – – Bit Symbol INT6Ctl.7 – INT6Ctl.6 – INT6Ctl.5 VFTIEN VDD fault interrupt enable. INT6Ctl.4 VFTINT VDD fault interrupt flag. INT6Ctl.3 I2CIEN When set = 1, the I When set =1, the I ...
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... DS_1209F_004 1.7.11 Keypad Interface Keypad Interface The 73S1209F supports a 30-button (6 row x 5 column) keypad (SPST Mechanical Contact Switches) The 73S1209F supports a 30-button (6 row x 5 column) keypad (SPST Mechanical Contact Switches) interface using 11 dedicated I/O pins. Figure 11 shows a simplified block diagram of the keypad interface using 11 dedicated I/O pins. Figure 11 shows a simplified block diagram of the keypad interface ...
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KCOL and KROW registers. The keypad interface uses a 1kHz clock derived from the 12MHz crystal. The clock is enabled by setting bit 6 – KBEN – in the and Clock Generation section) to carry out scanning and ...
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... Is (are) the key(s) Yes released ? (*) No KSCAN Register: Debouncing Time (*) Key release is cheked by looking for a low level on any row. 73S1209F Data Sheet KSTAT Register: Enable HW Scanning Enable Keypad Interrupt KSCAN Register: Debouncing Time KSIZE Register: Keypad Size Definition KSCAN Register: Scanning Rate ...
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Keypad Column Register (KCOL): 0xD1 This register contains the value of the column of a key detected as valid by the hardware. In bypass mode, this register firmware writes directly this register to carry out manual scanning. MSB – – ...
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... KEYDET cannot cause an interrupt. KEYDET can still get set even if the interrupt is not enabled. Rev. 1.2 0x00 Table 67: The KSCAN Register Function 0x00 Table 68: The KSTAT Register – – KEYCLK HWSCEN KEYDET KYDTEN Function 73S1209F Data Sheet LSB LSB 65 ...
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... ROWSIZ.2 Bit Symbol KSIZE.7 – KSIZE.6 – KSIZE.5 ROWSIZ.2 Defines the number of rows in the keypad. Maximum number is 6 given KSIZE.4 ROWSIZ.1 the number of row pins on the package. Allows for a reduced keypad size for scanning. KSIZE.3 ROWSIZ.0 KSIZE.2 COLSIZ.2 Defines the number of columns in the keypad. Maximum number is 5 KSIZE ...
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... These capacitors should be attached to the TBUS0:3 and ISBR signals. Rev. 1.2 Table 71: The KORDERH Register 5COL.0 4COL.2 4COL.1 Function (msb). 0x00 Table 72: The INT5Ctl Register Function 73S1209F Data Sheet 0x00 LSB 4COL.0 3COL.2 LSB KPIEN KPINT 67 ...
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... Smart Card Interface Function The 73S1209F integrates one ISO-7816 (T=0, T=1) UART, one complete ICC electrical interface as well as an external smart card interface to allow multiple smart cards to be connected using the Teridian 8010 family of interface devices. Figure 13 shows the simplified block diagram of the card circuitry (UART + interfaces), with detail of dedicated XRAM registers ...
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... If support for the auxiliary lines is necessary for the externa n eed to be handled manually through the USR GPIO pins. The external 8010 devices directly connect the I/O (SIO) and clock (SCLK) signals and control is handled via the I Figure 14 shows how multiple 8010 devices can be connected to the 73S1209F. VPC PRES PRES ...
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... ISO 7816 UART An embedded ISO 7816 (hardware) UART is provided to control communications between a smart card and the 73S1209F MPU. The UART can be shared between the one built-in ICC interface and the external ICC interface. Selection of the desired interface is made by register SCSel. Control of the ...
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... TS byte that begins the ATR response response is not provided within the pre-programmed timeout period, an interrupt is generated and the firmware can then take appropriate action, including instructing the 73S1209F to begin a deactivation sequence. Once commanded, the deactivation sequencer goes through the power down sequence as defined in the ISO 7816-3 specification ...
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Figure 15: Asynchronous Activation Sequence Timing Firmware sets VCCSEL delay or Card Event IO RST CLK CMDVCCnB VCC t1: Time after either a “card event” occurs or firmware sets the VCCSela and VCCSelb bits to 0 (see ...
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... There are two, two-byte FIFOs that are used to buffer transmit and receive data. During a T=0 processing parity error is detected by the 73S1209F during message reception, an error signal (BREAK) will be generated to the smart card. The byte received will be discarded and the firmware notified of the error. ...
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... CRC/LRC calculation (if required). 1.7.13.5 Synchronous Operation Mode The 73S1209F supports synchronous operation. When sync mode is selected for either interface, the CLK signal is generated by the ETU counter. The values in FDReg, SCCLK, and the desired sync CLK rate. There is only one ETU counter and therefore, in sync mode, the interface must ...
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... Special bits that are only active for sync mode include: SRXCtl, b7 “BIT9DAT”, STXCtl, b7 “I2CMODE”, and the definition of SCIE b7, was “WTOIEN”, becomes RLenIEN. Rev. 1.2 SCCtl and SCECtl register. The state of the data in the SCInt b7, was “WAITTO”, becomes RLenINT interrupt, and 73S1209F Data Sheet SPrtcol b6 “MODE9/8B”, 75 ...
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... Note that in Sync mode input is sampled on the rising edge of CLK. IO changes on the falling edge of CLK, either from the card or from the 73S1209F. The RST signal to the card is directly controlled by the RSTCRD bit (non-inverted) via the MPU and is shown as an example of a possible RST pattern. ...
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... RLength 5 Count MAX I2CMode = 1:ACK Bit (to/from card) I2CMode = 0: Data from TX fifo RLength Count MAX generate the Stop bit in Synchronous Mode. 73S1209F Data Sheet START Bit Data from TX FIFO RLen=0 Rlen=1 7 STOP Bit Min ½ ETU ...
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CLK Data from Card IO RLength Count RLength = 9 RLength Interrupt RX data Protection Bit Data (Bit 9) TX/RX Mode Bit TX = '1' 1._ Interrupt generated when Rlength counter is Max CLK RLength Count Rlen=8 RLength = 9 ...
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... Select Smart Card Interface – These bits select the interface that is using the IS0 UART. These bits do not activate the interface. Activation is performed by the VccCtl 1 = Enabled Disabled. When enabled, ISO UART is bypassed and the I/O line is controlled via the registers. 73S1209F Data Sheet LSB SELSC.0 BYPASS – register. SCCtl and ...
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Smart Card Interrupt Register (SCInt): 0xFE01 When the smart card interrupt is asserted, the firmware can read this register to determine the actual cause of the interrupt. The bits are cleared when this register is read. Each interrupt can be ...
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... RXDAEN Rx Data Available Interrupt Enable. SCIE.3 TXEVEN TX Event Interrupt Enable. SCIE.2 TXSNTEN TX Sent Interrupt Enable. SCIE.1 TXEREN TX Error Interrupt Enable. SCIE.0 RXEREN RX Error Interrupt Enable. Rev. 1.2 0x00 Table 75: The SCIE Register RXDAEN TXEVEN TXSNTEN TXEREN Function 73S1209F Data Sheet LSB RXEREN 81 ...
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... If not set, the deactivation sequence shall start when the VCCTMR times out. VccCtl.3 VCCOK (Read only). Indicates that V VccCtl.2 – VccCtl.1 – This bit controls the power-down mode of the 73S1209F circuit. VccCtl.0 SCPWRDN 1 = power down normal operation. 82 0x00 Table 76: The VccCtl Register RDYST VCCOK Function VCCSEL ...
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... VCCTMR(3:0) * 30.5μs. A value of 0000 results in no timeout, not zero time, and activation requires that RDYST is set and RDY VccTmr.0 VCCTMR.0 goes high. Rev. 1.2 0x0F Figure 15) in order for the activation sequence to continue. If VCC_OK Table 77: The VccTmr Register Function 73S1209F Data Sheet LSB 83 ...
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Card Status/Control Register (CRDCtl): 0xFE05 This register is used to configure the card detect pin (DETCARD) and monitor card detect status. This register be written to properly configure Debounce, Detect_Polarity (= 1), and the pull-up/down enable before ...
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... Cleared when read. This bit generates TXERR interrupt. Rev. 1.2 0x00 Table 79: The STXCtl Register TXEMTY TXUNDR LASTTX Function SCCtl (or SCECtl) register rather than the TX Protocol Mode Register 73S1209F Data Sheet LSB TX/RXB BREAKD for more detail. 85 ...
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STX Data Register (STXData): 0xFE07 MSB STXDAT.7 STXDAT.6 STXDAT.5 Bit STXData.7 STXData.6 STXData.5 Data to be transmitted to smart card. Gets stored in the TX FIFO and then extracted by the hardware and sent to the selected smart card. When ...
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... SRXData.7 SRXData.6 SRXData.5 SRXData.4 (Read only) Data received from the smart card. Data received from the smart card gets stored in a FIFO that is read by the firmware. SRXData.3 SRXData.2 SRXData.1 SRXData.0 Rev. 1.2 0x00 Table 82: The SRXData Register Function 73S1209F Data Sheet LSB 87 ...
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Smart Card Control Register (SCCtl): 0xFE0A This register is used to monitor reception of data from the smart card. MSB RSTCRD – Bit Symbol 1 = Asserts the RST (set RST = 0) to the smart card interface ...
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... SCLK SCLK enabled SCLK disabled. When disabled, SCLK level is SCECtl.0 SCLKOFF determined by SCLKLVL. This bit has no effect if in bypass mode. Rev. 1.2 0x00 Table 84: The SCECtl Register SIOD – – Function 73S1209F Data Sheet LSB SCLKLVL SCLKOFF 89 ...
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C4/C8 Data Direction Register (SCDIR): 0xFE0C This register determines the direction of the internal interface C4/C8 lines. After reset, all signals are tri-stated. MSB – – Bit Symbol SCDIR.7 – SCDIR.6 – SCDIR.5 – SCDIR.4 – SCDIR.3 C8D 1 = ...
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... ATR. Rev. 1.2 0x03 Table 86: The SPrtcol Register 0 TMODE CRCEN Function SCCtl register bits for direct firmware control. SCECtl register bits for direct firmware control. 73S1209F Data Sheet LSB CRCMS RCVATR SRXCtl 91 ...
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SC Clock Configuration Register (SCCLK): 0xFE0F This register controls the internal smart card (CLK) clock generation. MSB – – ICLKFS.5 ICLKFS.4 ICLKFS.3 ICLKFS.2 ICLKFS.1 ICLKFS.0 Bit Symbol SCCLK.7 – SCCLK.6 – SCCLK.5 ICLKFS.5 Internal Smart Card CLK Frequency Select – ...
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... Force Parity Error – enabled disabled. Used for test purposes. If SParCtl.0 FORCPE enabled, the UART will generate a parity error on a character received from the smart card. Rev. 1.2 0x00 Table 89: The SParCtl Register Function 73S1209F Data Sheet LSB INSPE FORCPE 93 ...
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Byte Control Register (SByteCtl): 0xFE12 This register controls the processing of characters and the detection of the TS byte. When receiving, a Break is asserted at 10.5 ETU after the beginning of the start bit. Break from the card is ...
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... Data Sheet LSB DVAL.1 DVAL.0 0101 0110 0111 1488 1860 1860⊕ 20⊕ 1101 1110 1111 2048 2048⊕ 2048⊕ 20 20⊕ ...
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Table 93: Divider Values for the ETU Clock Fi code 0000 Di 372 F→ code D↓ 0001 1 744 0010 2 372 0011 4 186 0100 8 93 1000 12 62 0101 16 47 1001 20 37 0110 32 23 ...
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... CRCEN is not set and in mode T1). They are available to the firmware to use if desired. Rev. 1.2 0xFF, (CRCLsB): 0xFE15 Table 94: The CRCMsB Register CRC.13 CRC.12 CRC.11 Table 95: The CRCLsB Register CRC.5 CRC.4 CRC.3 73S1209F Data Sheet 0xFF LSB CRC.10 CRC.9 CRC.8 LSB CRC.2 CRC.1 CRC.0 97 ...
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Block Guard Time Register (BGT): 0xFE16 This register contains the Extra Guard Time Value (EGT) most-significant bit. The Extra Guard Time indicates the minimum time between the leading edges of the start bit of consecutive characters. The delay is depends ...
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... These registers (BWTB0, BWTB1, BWTB2, BWTB3) are used to set the Block Waiting Time(27:0) (BWT). All of these parameters define the maximum time the 73S1209F will have to wait for a character from the smart card. These registers serve a dual purpose. When T=1, these registers are used to set up the block wait time ...
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ATR Timeout Registers (ATRLsB): 0xFE20 MSB ATRTO.7 ATRTO.6 ATRTO.5 MSB ATRTO.15 ATRTO.14 ATRTO.13 These registers (ATRLsB and ATRLsB) form the ATR timeout (ATRTO [15:0]) parameter. Time in ETU between the leading edge of the first character and leading edge of ...
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... SCESYN 0 DISPAR BRKGEN BRKDET DETTS DIRTS BRKDUR (1:0) FVAL(3:0) CRC(15:8) CRC(7:0) EGT(7:0) BWT(23:16) BWT(15:8) BWT(7:0) CWT(15:8) CWT(7:0) ATRTO(15:8) ATRTO(7:0) TSTO(7:0) RLen(7:0) 73S1209F Data Sheet SelSC(1:0) BYPASS TXEVNT TXSENT TXERR TXEVEN TXSNTEN TXERR VCCOK VCCTMR(3:0) DETPOL PUENB PDEN TXUNDR LASTTX TX/RXB RXFULL ...
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... Note: The V Fault factory default can be set to any threshold as defined by bits VDDFTH(2:0). The DD 73S1209F has the capability to burn fuses at the factory to set the factory default to any of these voltages. Contact Teridian for further details. 102 falls below the V DD 0x00 Table 109: The VDDFCtl Register – ...
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... SW_MOM S26 S27 S28 S29 S30 SW_MOM SW_MOM SW_MOM SW_MOM SW_MOM Figure 24: 73S1209F Typical PINpad, Smart Card Reader Application Schematic Rev. 1 12.000MHz C6 22pF TXD ISBR 19 67 COL4 SEC 20 66 USR7 RESET 21 ...
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... T5IN R1OUTBF R1IN R1OUT 9 20 R2IN R2OUT 11 18 R3IN R3OUT 3.3V 13 SERIAL ENB 14 SHDNB PORT Figure 25: 73S1209F Typical SIM / Smart Card Reader Application Schematic 104 12.000MHz C24 C25 22pF 22pF LED1 D3 C26 LED0 D4 10uF 3. TXD VDD 13 43 USR7 ...
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... Electrical Specification 3.1 Absolute Maximum Ratings Operation outside these rating limits may cause permanent damage to the device. The smart card interface pins are protected against short circuits to V Parameter DC Supply voltage Supply Voltage V PC Storage Temperature Pin Voltage (except card interface) ...
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Digital IO Characteristics These requirements pertain to digital I/O pin types with consideration of the specific pin function and configuration. The LED(1:0) pins have pull-ups that may be enabled. The Row pins have 100KΩ pull-ups. Symbol Parameter Voh Output ...
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Smart Card Interface Requirements Symbol Parameter Card Power Supply (V ) Regulator CC General conditions, -40°C < T < 85°C, 4.75V < V Card supply Voltage V CC including ripple and noise V V Ripple CCrip CC Card supply ...
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... Output rise time, fall times Input rise, fall times Internal pull-up resistor PU FD Maximum data rate MAX Reset and Clock for Card Interface, RST, CLK V Output level, high OH V Output level, low OL Output voltage when outside V INACT of session ...
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DC Characteristics Symbol Parameter I Supply Current DD I Supply Current supply current when V PCOFF PC 3.8 Voltage / Temperature Fault Detection Circuits Symbol Parameter V fault Voltage supervisor PCF PC threshold) ...
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Equivalent Circuits X12LIN ESD ENABLE Output Disable Data From circuit To circuit 110 VDD Figure 26: 12 MHz Oscillator Circuit VDD STRONG Figure 27: Digital I/O Circuit X12OUT ESD To circuit STRONG PFET PIN ESD NFET Rev. 1.2 ...
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Output Disable Data From circuit Pull-up Disable Output Disable Data From circuit To circuit Figure 29: Digital I/O with Pull Up Circuit Rev. 1.2 VDD STRONG PFET STRONG NFET Figure 28: Digital Output Circuit STRONG PFET STRONG NFET PIN ESD ...
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Output Disable Data From circuit To circuit Pull-down Enable Figure 30: Digital I/O with Pull Down Circuit To circuit 112 VDD STRONG PFET STRONG NFET ESD Figure 31: Digital Input Circuit PIN ESD VERY WEAK NFET PIN Rev. 1.2 ...
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Pull-up Disable Output Disable Data From circuit To circuit Output Disable Data From circuit To circuit Rev. 1.2 STRONG PFET STRONG NFET Figure 32: Keypad Row Circuit VDD 1200 OHMS MEDIUM PFET STRONG NFET Figure 33: Keypad Column Circuit VDD ...
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Pullup Disable Data From circuit To circuit Current Value Control PIN Figure 35: Test and Security Pin Circuit 114 VDD STRONG PFET STRONG NFET Figure 34: LED Circuit This buffer has a special input threshold: Vih>0.7*VDD ESD ...
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From circuit Rev. 1.2 To Comparator Input PIN ESD Figure 36: Analog Input Circuit VCC Figure 37: Smart Card Output Circuit STRONG ESD PFET PIN ESD STRONG NFET 115 ...
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From circuit To circuit To circuit Pull-down Enable Pull-up Enable To circuit 116 STRONG PFET 125ns DELAY STRONG NFET Figure 38: Smart Card I/O Circuit VERY WEAK NFET Figure 39: PRES Input Circuit VERY WEAK PFET Figure 40: PRES Input ...
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... ROW1 22 USR6 23 ROW2 24 GND 25 N/C 26 N/C 27 VDD 28 USR5 29 USR4 30 USR3 31 USR8 32 USR2 33 ROW3 34 Rev. 1.2 TERIDIAN 73S1209F Figure 41: 73S1209F Pinout CAUTION: Use handling procedures necessary for a static sensitive component ISBR 68 SEC 67 RESET 66 VDD 65 PRES AUX1 62 AUX2 61 VCC 60 RST 59 GND 58 CLK 57 PRESB 56 VPC ...
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... Package Pin Designation (44-pin QFN) TXD 12 USR7 13 USR6 14 GND 15 N/C 16 N/C 17 VDD 18 USR5 19 USR4 20 USR3 21 USR2 22 118 CAUTION: Use handling procedures necessary for a static sensitive component TERIDIAN 73S1209F Figure 42: 73S1209F Pinout VDD 44 PRES AUX1 41 AUX2 40 VCC 39 RST 38 GND 37 CLK 36 PRESB 35 VPC 34 Rev. 1.2 ...
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... Controlling dimensions are in mm. Controlling dimensions are in mm. 8.00 7. TOP VIEW TOP VIEW 8.00 0.42 0.24/0.60 6.30 6.15/6.45 0.45 0.42 0.24/0.60 6.30 6.15/6.45 6.40 BOTTOM VIEW Rev. 1.2 7.75 8.00 PIN#1 ID R0. 6.40 8.00 Figure 43: 73S1209F 68 QFN Pinout 0.65 0.85 0.2 0.00/0.05 12° SEATING PLANE SIDE VIEW 0.00/0.05 0.20 0.15/0.25 SECTION "C-C" SCALE: NONE TERMINAL TIP 0.40 FOR ODD TERMINAL/SIDE 119 ...
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... Notes: 5.1mm x 5.1mm exposed pad area must remain UNCONNECTED (clear of PCB traces or vias). Controlling dimensions are in mm. 7.00 6. TOP VIEW 7.00 0.42 0.24/0.60 5.10 4.95/5.25 0.45 0.42 0.24/0.60 5.10 4.95/5.25 5.00 BOTTOM VIEW 120 6.75 7.00 PIN#1 ID R0. 5.00 7.00 Figure 44: 73S1209F 44 QFN Pinout 0.65 0.85 0.2 0.00/0.05 12° SEATING PLANE SIDE VIEW 0.00/0.05 0.23 0.18/0.30 SECTION "C-C" SCALE: NONE TERMINAL TIP 0.50 FOR ODD TERMINAL/SIDE Rev. 1.2 ...
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... Evaluation Board User’s Guide 73S12xxF Software User’s Guide 73S12xxF Synchronous Card Design Application Note 7 Contact Information For more information about Teridian Semiconductor products or to check the availability of the 73S1209F, contact us at: 6440 Oak Canyon Road Suite 100 Irvine, CA 92618-5201 ...
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Revision History Revision Date Description 1.0 4/4/2007 First publication. 1.1 11/7/2007 In In and 32-cycle references. In must be bound between a value The possible crystal or external clock are shown in Table 12.“ to “Mcount ...
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In Async Operation table into three primary types. These are commonly referred to as 2-wire, 3-wire and I2C synchronous cards. Each card type requires different control and timing and therefore requires different algorithms to access. Teridian has created ...