73S1209F Maxim, 73S1209F Datasheet - Page 84
73S1209F
Manufacturer Part Number
73S1209F
Description
The 73S1209F is a self-contained, SoC smart card reader IC that is an ideal solution for serially connected ISO 7816 design
Manufacturer
Maxim
Datasheet
1.73S1209F.pdf
(123 pages)
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Card Status/Control Register (CRDCtl): 0xFE05
This register is used to configure the card detect pin (DETCARD) and monitor card detect status. This
register be written to properly configure Debounce, Detect_Polarity (= 0 or = 1), and the pull-up/down
enable before setting CDETEN. The card detect logic is functional even without smart card logic clock.
When the PWRDN bit is set = 1, no debounce is provided but card presence is operable.
84
CRDCtl.7
CRDCtl.6
CRDCtl.5
CRDCtl.4
CRDCtl.3
CRDCtl.2
CRDCtl.1
CRDCtl.0
MSB
DEBOUN CDETEN
Bit
DEBOUN
CDETEN
DETPOL
CARDIN
Symbol
PUENB
PDEN
–
–
Debounce – When set = 1, this will enable hardware de-bounce of the
card detect pin. The de-bounce function shall wait for 64ms of stable card
detect assertion before setting the CARDIN bit. This counter/timer uses
the keypad clock as a source of 1kHz signal. De-assertion of the CARDIN
bit is immediate upon de-assertion of the card detect pin(s).
Card Detect Enable – When set = 1, activates card detection input.
Default upon power-on reset is 0.
Detect Polarity – When set = 1, the DETCARD pin shall interpret a logic 1
as card present.
Enable pull-up current on DETCARD pin (active low).
Enable pull-down current on DETCARD pin.
Card Inserted – (Read only). 1 = card inserted, 0 = card not inserted. A
change in the value of this bit is a “card event.” A read of this bit indicates
whether smart card is inserted or not inserted in conjunction with the
DETPOL setting.
–
Table 78: The CRDCtl Register
–
DETPOL
0x00
Function
PUENB
PDEN
CARDIN
LSB
Rev. 1.2
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