73S1210F Maxim, 73S1210F Datasheet - Page 28

• Manufacturer Part Number: 73S1210F
• Description: The 73S1210F is a versatile and economical CMOS system-on-chip (SoC) device intended for smart card reader applications
• Manufacturer: Maxim

73S1210F Data Sheet
When the PWRDN bit is set, the clock subsystem will provide a delay of 32 MPUCLK cycles to allow the
program to set the STOP bit in the
core before the analog circuits shut down (high speed oscillator, VCO/PLL, voltage reference and bias
circuitry, etc.). The PDMUX bit in SFR
configure the wake up interrupt logic. The power down mode is de-asserted by any of the interrupts
connected to external interrupts 0, 4 and 5 (external USR[0:7], smart card and Keypad). These interrupt
sources are OR’ed together and routed through some delay logic into INT0 to provide this functionality.
The interrupt will turn on the power to all sections that were shut off and start the clock subsystem. After
the clock subsystem clocks start running, the MPUCLK begins to clock a 512 count delay counter. When
the counter times out, the interrupt will then be active on INT0 and the program can resume. Figure 7
shows the detailed logic for waking up the 73S1210F from a power down state using these specific
interrupt sources. Figure 8 shows the timing associated with the power down mode.
28
Notes:
1. The counters are clocked by the MPUCLK
2. TC - Terminal count (high at overflow)
3. CE - Count enable
USR0
USR1
USR2
USR3
USR4
USR5
USR6
USR7
USR[7:0] Control
USRxINTSrc set to
4(ext INT0 high)
6(ext INT0 low)
or
INT4
INT5
RESETB
Figure 7: Detail of Power Down Interrupt Logic
PCON
INT5Ctl
D
CLR
register. This delay will enable the program to properly halt the
PDMUX
(FF94h:bit7)
RESETB
Q
should be set prior to setting the PWRDN bit in order to
PWRDN
(FFF1h:bit7)
0
1
RESETB
CE
5 BIT CNTR
CLR
TC
INT0
CE
9 BIT CNTR
MPU
CLR
TC
PWRDN_analog
DS_1210F_001
Rev. 1.4