73S8024C Maxim, 73S8024C Datasheet
73S8024C
Related parts for 73S8024C
73S8024C Summary of contents
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... Simplifying System Integration™ DESCRIPTION The Teridian 73S8024C is a single smart card interface IC. It provides full electrical compliance with ISO-7816-3, EMV 4.0 and NDS specifications Interfacing with the system controller is done through the control bus, composed of digital inputs to control the interface, and one interrupt output to inform the system controller of the card presence and faults ...
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... FAULT CC V FAULT DD V FAULT CC R-C Int_Clk OSC. DIGITAL CIRCUITRY & ISO-7816-3 SEQUENCER CLOCK TEMP FAULT ICC I/O BUFFERS Pin number reference to SO28 Package Figure 1: 73S8024C Block Diagram DS_8024C_023 LIN VDD GND 14 DC-DC GND CONVERTER 17 VCC ICC RESET 16 BUFFER RST ICC CLOCK ...
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... Figure 5: Deactivation Sequence ............................................................................................................... 11 Figure 6: Timing Diagram – Management of the Interrupt Line OFF .......................................................... 11 Figure 7: I/O and I/OUC State Diagram ...................................................................................................... 12 Figure 8: I/O – I/OUC Delays: Timing Diagram ........................................................................................... 12 Figure 9: 73S8024C Typical Application Schematic ................................................................................... 13 Figure 10: DC – DC Converter efficiency (V Figure 11: DC – DC Converter Efficiency (V Figure 12: 28 Lead SO ................................................................................................................................ 19 Table Table 1: Choice of VCC Pin Capacitor ...
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... Data Sheet 1 Pin Description 1.1 Card Interface Pin Name Description (SO Card I/O: Data signal to/from card. Includes a pull-up resistor to V AUX1 13 AUX1: Auxiliary data signal to/from card. Includes a pull-up resistor to V AUX2 12 AUX2: Auxiliary data signal to/from card. Includes a pull-up resistor to V ...
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... Power Down control input (active high): When Power Down (PD) mode is activated; all internal analog functions are disabled to place the 73S8024C in its lowest power consumption mode. The PD mode is allowed only out of a card session (= PWRDN high is not taken into account when CMDVCC = 0). Must be tied to ground when the power down function is not used ...
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... Power Down: The PWRDN pin is a digital input that allows the host controller to put the 73S8024C in its Power Down state. This pin can only be activated out of a card session. 3 Oscillator The 73S8024C device has an on-chip oscillator that can generate the smart card clock using an external crystal (connected between the pins XTALIN and XTALOUT) to set the oscillator frequency ...
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... Table 1: Choice of VCC Pin Capacitor Voltage CC Max Transient Current Charge 4 nAs 4 nAs Table 1: Choice of VCC Pin Capacitor 73S8024C Data Sheet is greater than the set point for high as 100 mA. CC minimum voltage and the CC Table 1 shows the Application Capacitor ...
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... DC-DC converter, to put the 73S8024C in its lowest power consumption mode. PD mode is only allowed in the deactivated condition (out of a card session, when the CMDVCC signal is driven high from the host controller) ...
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... OFF PWRDN Internal RC OSC CMDVCC Figure 2: Power Down Mode Operation 8 Activation Sequence The 73S8024C smart card interface IC has an internal 10 ms delay at power-on reset or upon application or upon exit of Power-Down mode. The card interface may only be activated when OFF > DDF high which indicates a card is present ...
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... Data Sheet The following steps and Figure 4 when the system controller pulls CMDVCC low while RSTIN is high: 1. CMDVCC is set low. 2. Next, the internal V control circuit checks the presence the card becomes valid during this time. If not, OFF goes low to report a fault to ...
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... Figure 6: Timing Diagram – Management of the Interrupt Line OFF Rev. 1 ≥ 0.5 µ < 100 µ Figure 5: Deactivation Sequence OFF is low by card extracted within card session 73S8024C Data Sheet t 5 OFF is low by any fault within card session 11 ...
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... Data Sheet 11 I/O Circuitry and Timing The I/O, AUX1, and AUX2 pins are in the low state after power on reset and they are in the high state when the activation sequencer turns on the I/O reception state. See more details on when the I/O reception is on. The state of the I/OUC, AUX1UC, and AUX2UC is high after power on reset. Within a card session and when the I/O reception state is on, the first I/O line on which a falling edge is detected becomes the input I/O line and the other becomes the output I/O line ...
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... AUX1 RST 14 GND CLK 73S8024C SO28 R2 20K Card detection switch is normally closed. Smart Card Connector Figure 9: 73S8024C Typical Application Schematic 73S8024C Data Sheet See NOTE 2 AUX2UC_to/f rom_uC AUX1UC_to.f rom_uC IOUC_to/f rom_uC VDD See NOTE 1 See NOTE 3 External_clock_f rom uC R3 Rext2 - ...
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... Data Sheet 13 Electrical Specification 13.1 Absolute Maximum Ratings Operation outside these rating limits may cause permanent damage to the device. Parameter Supply Voltage V DD Input Voltage for Digital Inputs Storage Temperature Pin Voltage (except LIN and card interface) Pin Voltage (LIN) Pin Voltage (card interface) ESD Tolerance – ...
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... CC selected, L=10 µH 100 µF 0. µ 73S8024C Data Sheet Typ. Max. Unit 0.1 V 0.4 V 5.25 V 3.2 V 5.25 V 3.2 V 5. 125 180 mA 0.15 0.25 V/µs 0.3 0.5 V/µs µF 1 3.3 µH ...
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... Data Sheet 100 Figure 10: DC – DC Converter efficiency (V Output current 100 Figure 11: DC – DC Converter Efficiency (V Output current 1011B01 Converter efficiency (VCC 5V) Converter Efficiency (V 2.7V 3.0V 3.3V 3. Icc [mA ...
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... 200 µ for CLK, L 10 200 pF for RST, L 10% to 90% C =35 pF, L ≤ MHz CLK 73S8024C Data Sheet Min. Typ. Max. Unit 0.3 1 ...
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... Data Sheet 13.4 Digital Signals Symbol Parameter Digital I/O except for OSC I/O VIL Input Low Voltage VIH Input High Voltage VOL Output Low Voltage VOH Output High Voltage ROUT Pull-up resistor, OFF |IIL1| Input Leakage Current Oscillator (XTALIN) I/O Parameters V Input Low Voltage - XTALIN ...
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... DS_8024C_023 14 Mechanical Drawings (28-SO) PIN NO. 1 BEVEL .715 (18.161) .695 (17.653) .110 (2.790) .092 (2.336) Rev. 1.3 .050 TYP. (1.270) .305 (7.747) .285 (7.239) .0115 (0.29) .003 (0.076) .016 nom (0.40) Figure 12: 28 Lead SO 73S8024C Data Sheet .420 (10.668) .390 (9.906) .335 (8.509) .320 (8.128) 19 ...
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... PRES I/O AUX2 AUX1 GND 73S8024C (Top View) Figure 11: 73S8024C 28-SO Pin Out DS_8024C_023 AUX2UC AUX1UC I/OUC XTALOUT XTALIN OFF GND VDD RSTIN CMDVCC VDDF_ADJ VCC RST CLK Rev. 1.3 ...
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... Part Description 73S8024C-SO 28-pin Lead-Free SO 73S8024C-SO 28-pin Lead-Free SO Tape / Reel 17 Related Documentation The following 73S8024C documents are available from Teridian Semiconductor Corporation: 73S8024C Data Sheet (this document) 73S8024C Demo Board User’s Guide 18 Contact Information For more information about Teridian Semiconductor products or to check the availability of the ...
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... Data Sheet Revision History Revision Date Description 1.0 6/21/2005 First publication. 1.1 7/15/2005 Removed QFN package information. 1.2 12/5/2007 Add ISO and EMV logos, remove leaded package option, update 28SO package dimension. 1.3 4/3/2009 Remove all references to VPC as VPC must be tied to VDD. © 2009 Teridian Semiconductor Corporation. All rights reserved. ...