73S8024C Maxim, 73S8024C Datasheet - Page 6

• Manufacturer Part Number: 73S8024C
• Description: The 73S8024C is a single smart card interface IC, compliant to the electrical requirements of ISO 7816-3 and EMV 4
• Manufacturer: Maxim

73S8024C Data Sheet
2 System Controller Interface
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3 Oscillator
The 73S8024C device has an on-chip oscillator that can generate the smart card clock using an external
crystal (connected between the pins XTALIN and XTALOUT) to set the oscillator frequency. When the
card clock signal is available from another source, it can be connected to the pin XTALIN, and the pin
XTALOUT should be left unconnected.
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2 digital inputs allow direct control of the card interface from the host as follows:
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
The card I/O and Reset signals have their corresponding controller I/Os to be connected directly to
the host:
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

2 digital inputs control the card clock frequency division rate: CLKDIV1 and CLKDIV2 define the card
clock frequency, from the input clock frequency (crystal or external clock). The division rate is defined
as follows:
Interrupt output to the host: As long as the card is not activated, the OFF pin informs the host about
the card presence only (low = no card in the reader). When CMDVCC is set low (Card activation
sequence requested from the host), a low level on OFF means a fault has been detected (e.g. card
removed during a card session, or voltage fault, or thermal / over-current fault) that automatically
initiates a deactivation sequence.
Power Down: The PWRDN pin is a digital input that allows the host controller to put the 73S8024C in
its Power Down state. This pin can only be activated out of a card session.
Pin CMDVCC: When low, starts an activation sequence if a card is present.
Pin 5V/#V: Defines the card voltage.
Pin RSTIN: controls the card reset signal (when enabled by the sequencer).
Pin I/OUC: data transfer to card I/O contact.
Pins AUX1UC and AUX2UC (auxiliary I/O lines associated to the auxiliary I/O lines to be
connected to the C4 and C8 card connector contacts).
When the division rate is equal to 1 (CLKDIV2 =0 and CLKDIV1 = 1), the duty-cycle of the
card clock depends on the duty-cycle and waveform of the signal applied on the pin XTALIN.
When other division rates are used, the 73S8024C circuitry guarantees a duty-cycle in the
range 45% to 55%, conforming to ISO-7816-3, EMV 4.0 and NDS specifications.
CLKDIV2
0
0
1
1
CLKDIV1
0
1
0
1
⅛
¼ XTAL
½ XTAL
XTAL
CLK
XTAL
DS_8024C_023
Rev. 1.3