MAX7320 Maxim, MAX7320 Datasheet - Page 7

• Manufacturer Part Number: MAX7320
• Description: The MAX7320 2-wire serial-interfaced peripheral features eight push-pull outputs with selectable power-up logic states
• Manufacturer: Maxim

Table 3. MAX7320 Address Map
The RST input clears the serial interface in case of a
hung bus, terminating any serial transaction to or from
the MAX7320.
When the MAX7320 is read through the serial interface,
the actual logic states at the ports are read back.
Output port power-up logic states are selected by the
address select inputs AD0 and AD2. Ports default to
logic-high or logic-low on power-up in groups of four
(see Table 3).
The RST input voids any I
MAX7320 and forces the MAX7320 into the I
condition. A reset does not change the contents of the
output register. RST is overvoltage tolerant to +5.5V.
When the serial interface is idle, the MAX7320 automat-
ically enters standby mode, drawing minimal supply
current.
Address inputs AD0 and AD2 determine the MAX7320
slave address and set the power-up output logic states.
Power-up logic states are set in groups of four (see
Table 3). The MAX7320 uses a different range of slave
CONNECTION
GND
GND
GND
GND
AD2
SDA
SDA
SDA
SDA
SCL
SCL
SCL
SCL
V+
V+
V+
V+
I
2
PIN
C Port Expander with Eight Push-Pull Outputs
GND
GND
GND
GND
AD0
SDA
SDA
SDA
SDA
SCL
SCL
SCL
SCL
V+
V+
V+
V+
A6
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
_______________________________________________________________________________________
Slave Address and Power-Up
A5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
2
C transaction involving the
Default Logic States
DEVICE ADDRESS
A4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Standby Mode
A3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
RST Input
A2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
2
C STOP
A1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
addresses (101xxxx) than the MAX7319, MAX7321,
MAX7322, and MAX7323 (110xxxx).
The MAX7320 slave address is determined on each I
transmission, regardless of whether the transmission is
actually addressing the MAX7320. The MAX7320 distin-
guishes whether address inputs AD0 and AD2 are con-
nected to SDA or SCL instead of fixed logic levels V+
or GND during this transmission. This means that the
MAX7320 slave address can be configured dynamical-
ly in the application without cycling the device supply.
On initial power-up, the MAX7320 cannot decode the
address inputs AD0 and AD2 fully until the first I
transmission. AD0 and AD2 initially appear to be con-
nected to V+ or GND. This is important because the
address selection determines the power-up logic levels
of the output ports. However, at power-up, the I
and SCL bus interface lines are high impedance at the
pins of every device (master or slave) connected to the
bus, including the MAX7320. This is guaranteed as part
of the I
and AD2 that are connected to SDA or SCL normally
appear at power-up to be connected to V+. The power-
up output state selection logic uses AD0 to select the
power-up state for ports O3–O0, and uses AD2 to
select the power-up state for ports O7–O4. The rule is
that a logic-high, SDA, or SCL connection selects a
O7
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
2
C specification. Therefore, address inputs AD0
O6
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
OUTPUTS POWER-UP DEFAULT
O5
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
O4
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
O3
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
O2
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
O1
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
2
C SDA
O0
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
2
2
C
C
7