MAX7320 Maxim, MAX7320 Datasheet - Page 8

• Manufacturer Part Number: MAX7320
• Description: The MAX7320 2-wire serial-interfaced peripheral features eight push-pull outputs with selectable power-up logic states
• Manufacturer: Maxim

logic-high power-up state, and a logic-low selects a
logic-low power-up state for each set of four ports (see
Table 3). The output power-up logic level configuration
is correct for a standard I
or SCL appear to be connected to V+ by the external
I
There are circumstances where the assumption that
SDA = SCL = V+ on power-up is not true; for example,
in true hot-swap applications in which there is legiti-
mate bus activity during power-up. Also, if SDA and
SCL are terminated with pullup resistors to a different
supply voltage than the MAX7320’s supply, and if that
pullup supply rises later than the MAX7320’s, then SDA
or SCL may appear at power-up to be connected to
GND. In such applications, use the four address combi-
nations that are selected by connecting address inputs
AD0 and AD2 to GND or V+ (shown in bold in Table 3).
These selections are guaranteed to be correct at
power-up, independent of SDA and SCL behavior. If
one of the other 12 address combinations is used, be
aware that unexpected port power-up default states
may occur until the first I
not necessarily the MAX7320).
Write one byte to the MAX7320 to set all output port
states simultaneously.
The MAX7320 operates as a slave that sends and
receives data through an I
uses a serial data line (SDA) and a serial clock line
(SCL) to achieve bidirectional communication between
master(s) and slave(s). A master initiates all data trans-
I
Figure 1. 2-Wire Serial-Interface Timing Details
8
2
C pullups.
2
_______________________________________________________________________________________
C Port Expander with Eight Push-Pull Outputs
SDA
SCL
t
HD,STA
START CONDITION
t
LOW
2
C transmission (to any device,
2
C configuration, where SDA
2
t
R
C interface. The interface
t
SU,DAT
t
HIGH
Serial Interface
t
F
Serial-Addressing
Port Outputs
t
HD,DAT
t
VD,DAT
t
REPEATED START CONDITION
SU,STA
fers to and from the MAX7320, and generates the SCL
clock that synchronizes the data transfer (Figure 1).
SDA operates as both an input and an open-drain output.
A pullup resistor, 4.7kΩ (typ), is required on SDA. SCL
operates only as an input. A pullup resistor, 4.7kΩ (typ),
is required on SCL if there are multiple masters on the 2-
wire interface, or if the master in a single-master system
has an open-drain SCL output.
Each transmission consists of a START condition sent
by a master, followed by the MAX7320’s 7-bit slave
address plus R/W bit, one or more data bytes, and
finally a STOP condition (Figure 2).
Both SCL and SDA remain high when the interface is
not busy. A master signals the beginning of a transmis-
sion with a START (S) condition by transitioning SDA
from high to low while SCL is high. When the master
has finished communicating with the slave, the master
issues a STOP (P) condition by transitioning SDA from
low to high while SCL is high. The bus is then free for
another transmission (Figure 2).
One data bit is transferred during each clock pulse.
The data on SDA must remain stable while SCL is high
(Figure 3).
Figure 2. START and STOP Conditions
SDA
SCL
CONDITION
START
S
t
HD,STA
START and STOP Conditions
t
SU,STO
CONDITION
STOP
t
BUF
CONDITION
Bit Transfer
START
CONDITION
STOP
P