MAX7365 Maxim, MAX7365 Datasheet - Page 9

• Manufacturer Part Number: MAX7365
• Description: The MAX7365 is an I²C-interfaced peripheral that provides microprocessors with management of up to 56 key switches
• Manufacturer: Maxim

The Configuration register controls the I
out feature, enables the key-release indicator, enables
autowake, and determines how INT is deasserted. Write
to bit D7 to put the device into sleep or operating mode.
Autosleep and autowake, when enabled, also change the
status of D7
The Key-Switch Debounce register sets the keypress and
key-release time for each debounce cycle. Bits D[3:0]
set the debounce time for keypresses, while bits D[7:4]
set the debounce time for key releases. Both debounce
times are configured in increments of 2ms starting at 1ms
and ending at 31ms
The Key-Switch Interrupt register contains information
related to the settings of the interrupt request function,
as well as the status of the INT output. If bits D[7:0]
are set to 0x00, INT is disabled. There are two types of
interrupts, the FIFO-based interrupt and the time-based
interrupt. Set bits D[4:0] to assert interrupts at the end
of the selected number of debounce cycles following
a key event
debounce cycles. Setting bits D[7:5] sets the FIFO-
based interrupt when there are 2–14 key events stored
in the FIFO. Both interrupts can be configured simultane-
ously, and INT asserts depending on which condition is
met first. INT deasserts depending on the status of bit D5
in the Configuration register.
The device’s autorepeat feature notifies the host that at
least one key has been pressed for a continuous period.
The Autorepeat register enables or disables this feature,
sets the time delay after the last key event before the key
repeat code (0x7E) is entered into the FIFO, and sets
the frequency at which the key-repeat code is entered
into the FIFO thereafter. The autorepeat code continues
to be entered in the FIFO at the frequency set by bits
D[3:0] until another key event is recorded. The key being
pressed is not entered again into the FIFO. Following
the key-release event, if any keys are still pressed, the
device restarts the autorepeat sequence. Bit D7 speci-
fies whether the autorepeat function is enabled with 0
denoting autorepeat disabled, and 1 denoting autore-
peat enabled. Bits D[3:0] specify the autorepeat delay in
(Table
(Table
Key-Switch Autorepeat Register (0x05)
Key-Switch Debounce Register (0x02)
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Key-Switch Interrupt Register (0x03)
7).
9). This number ranges from 1–31
(Table
Configuration Register (0x01)
8).
Key-Switch Controller with GPIO Ports
2
C bus time-
1MHz I
terms of debounce cycles, ranging from 8–128 debounce
cycles
or frequency ranging from 4–32 debounce cycles.
Autosleep puts the device in sleep mode to draw
minimal current. When enabled, the device enters sleep
mode if no keys are pressed for the autoshutdown time
(Table
Bits D[7:4] set the row size of the key-switch array, and
bits D[3:0] set the column size of the key-switch array
(see
used. The key-switch array should be connected begin-
ning at ROW0 and COL0. If not used as a key-switch-
matrix pin, the pin can function as a GPI port, if enabled.
In sleep mode, the device draws minimal current. Switch-
matrix current sources are turned off and become high.
When autosleep is enabled, key-switch inactivity for a
period longer than the autosleep time puts the part into
sleep mode (FIFO data is maintained). Writing a 1 to
D7 in the Configuration register (0x01) or a keypress
can take the device out of sleep mode. Bit D7 in the
Configuration register gives the sleep-mode status and
can be read at any time.
To place the device in sleep mode, clear bit D7 in the
Configuration register. The device is in sleep mode
after power-on reset (POR). In sleep mode, the keyscan
controller is disabled and the device draws minimal cur-
rent. No additional supply current is drawn if no keys are
pressed. All switch-matrix current sources are turned
off, and the row outputs (ROW7–ROW0) are low and the
column outputs (COL6–COL0) become high.
To take the device out of sleep mode and into operating
mode, cause a low-to-high transition in bit D7 by setting it
to a 1 in the Configuration register. The keyscan control-
ler FIFO buffers are cleared and key monitoring starts.
Note that rewriting the Configuration register bit D7 to a
1, when bit D7 is already a 1, does not clear the FIFOs.
The FIFOs are only cleared when the device is changing
state from shutdown to operating mode.
In sleep mode, the internal oscillator is disabled and the
I
2
C timeout features are disabled.
Table
11).
(Table
12). Set the bits to 0 if no key switches are
2
10). Bits D[6:4] specify the autorepeat rate
C-Interfaced 8 x 7
Key-Switch Array Size Register (0x30)
Key-Switch Autosleep Mode
Autosleep Register (0x06)
MAX7365