MAX7370 Maxim, MAX7370 Datasheet - Page 15

• Manufacturer Part Number: MAX7370
• Description: The MAX7370 I²C-interfaced peripheral provides microprocessors with management of up to 64 key switches, with optional GPIO and PWM-controlled LED drivers
• Manufacturer: Maxim

with I
The device operates as a slave that sends and receives
data through an I
interface uses a serial-data line (SDA) and a serial-
clock line (SCL) to achieve bidirectional communication
between master(s) and slave(s). A master (typically a
microcontroller) initiates all data transfers to and from the
device and generates the SCL clock that synchronizes
the data transfer.
The device’s SDA line operates as both an input and an
open-drain output. A pullup resistor, typically 4.7kω, is
required on SDA. The device’s SCL line operates only as
an input. A pullup resistor is required on SCL if there are
multiple masters on the two-wire interface, or if the master
in a single-master system has an open-drain SCL output.
Each transmission consists of a START (S) condition
(Figure
slave address plus R/W bit, a register address byte, one
or more data bytes, and finally, a STOP (P) condition.
Both SCL and SDA remain high when the interface is not
busy. A master signals the beginning of a transmission
Figure 2. START and STOP Conditions
Figure 3. Bit Transfer
8 x 8 Key-Switch Controller and LED Driver/GPIOs
2) sent by a master, followed by the device’s 7-bit
SDA
SCL
2
C Interface and High Level of ESD Protection
SDA
SCL
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CONDITION
2
C-compatible two-wire interface. The
START
START and STOP Conditions
S
DATA LINE STABLE;
Serial Addressing
DATA VALID
CHANGE OF DATA
ALLOWED
with a START condition by transitioning SDA from high
to low while SCL is high. When the master has finished
communicating with the slave, it issues a STOP condition
by transitioning SDA from low to high while SCL is high.
The bus is then free for another transmission.
One data bit is transferred during each clock pulse
(Figure
SCL is high.
The acknowledge bit is a clocked 9th bit
the recipient uses to handshake receipt of each byte of
data. Thus, each byte transferred effectively requires 9
bits. The master generates the 9th clock pulse, and the
recipient pulls down SDA during the acknowledge clock
pulse; therefore, the SDA line is stable low during the
high period of the clock pulse. When the master is trans-
mitting to the device, the device generates the acknowl-
edge bit because the device is the recipient. When the
device is transmitting to the master, the master generates
the acknowledge bit because the master is the recipient.
3). The data on SDA must remain stable while
MAX7370
CONDITION
STOP
P
Acknowledge
(Figure
Bit Transfer
4), which