EL4511CUZ Intersil, EL4511CUZ Datasheet
EL4511CUZ
Specifications of EL4511CUZ
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EL4511CUZ Summary of contents
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... Note) (Pb-Free) EL4511CUZ-T7 24-Pin QSOP 7” (See Note) (Pb-Free) EL4511CUZ-T13 24-Pin QSOP 13” (See Note) (Pb-Free) NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations ...
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Absolute Maximum Ratings (T A Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . (V Pin Voltage ...
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Electrical Specifications otherwise specified. (Continued) PARAMETER DESCRIPTION REFERENCE OSCILLATOR F Reference Input Frequency IN F Crystal Frequency XTAL CONTROL INTERFACE SIGNALS PDWN, SDENB, SCL AND SDA V Input Logic High Threshold HIGH V Input Logic Low ...
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Pin Descriptions PIN NUMBER PIN NAME 1 XTAL 2 VBLANK 3 SYNCLOCK 4 PWDN 5 SDENB 6 SCL 7 SDA 8 GNDD1 9 HIN 10 SYNCIN 11 VERTIN 12 LEVEL 13 GNDA1 14 VCCA1 15 VCCA2 16 GNDA2 17 GNDD2 ...
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VCCA1 VERTICAL SYNC VERTIN SLICING COMPOSITE SYNC SYNCIN ANALOG HORIZONTAL SYNC HIN PROCESSING POWER DOWN PDWN LOW ACTIVE SERIAL SDENB DATA ENABLE SERIAL CLOCK SCL SERIAL I/F SERIAL DATA SDA GNDA1 5 EL4511 VCCD & DIGITAL PROCESSING RESET RATE REFERENCE ...
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COMPOSITE VIDEO INPUT, FIELD ONE Start of H Sync Field One Interval Pre-Equalizing .H Pulse Interval SYNC OUT OUTPUT V OUTPUT OUT ODD/EVEN OUTPUT BACKPORCH OUTPUT H OUTPUT OUT V BLANK Notes: b. The composite sync output ...
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COMPOSITE VIDEO INPUT, BEGINNING OF FIELD ONE 622 623 SYNCOUT OUTPUT V OUTPUT OUT ODD/EVEN OUTPUT BACKPORCH OUTPUT H OUTPUT OUT V BLANK OUTPUT Notes: b. The composite sync output reproduces all the video input sync pulses, with a propagation ...
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SYNCIN 1123 1124 1125 SYNCOUT H OUT BACKPORCH V OUT V BLANK ODD/EVEN SYNCIN 560 561 562 SYNCOUT H OUT BACKPORCH V OUT V BLANK ODD/EVEN FIGURE 6. EXAMPLE OF HDTV 1080I/30 LINE COMPOSITE VIDEO: INTERLACED, ODD & EVEN FIELD ...
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FIGURE 7. HDTV 1080I/25 LINE COMPOSITE VIDEO: INTERLACED ODD & EVEN FIELD (1250 LINES) 9 EL4511 Default 20 Lines Default 20 Lines FN7009.8 November 12, 2010 ...
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Timing Diagram 1 - Example of Horizontal Interval 525/625 Line Composite CONDITIONS CCA1 CCA2 INPUT DYNAMIC SYNC LEVEL RANGE 0.5V-2V (@V =5V) SYNC IN CCA1 0.5V-1V (@V =3.3V) CCA1 td SYNCOUT SYNC OUT td H OUT BACKPORCH ...
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Timing Diagram 2 - Example of Horizontal Interval 525/625 Line Composite CONDITIONS CCA1 CA2 INPUT SYNC LEVEL DYNAMIC RANGE 0.5V-2V SYNC IN (@V =5V) CCA1 0.5V-1V (@V =3.3V) CCA1 td SYNCOUT SYNC OUT td H OUT BACKPORCH ...
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Timing Diagram 3 - Example of Horizontal Interval (HDTV) (720p) CONDITIONS CCA1 CCA2 SYNCIN td SYNCOUT SYNC OUT H OUT BACKPORCH H Timing for HDTV, No Filter (using 720p input signal) PARAMETER DESCRIPTION td SYNCOUT Timing Relative ...
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Timing Diagram 4 - Example of Horizontal Interval (HDTV) CONDITIONS CCA1 CCA2 SYNCIN td SYNCOUT SYNC OUT H OUT BACKPORCH H Timing for HDTV, With Filter (using 720p input) PARAMETER DESCRIPTION td SYNCOUT Timing Relative to Input ...
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Operation Summarized Table Default register settings. All with no external analog filter. No Mode setting. 525/625 PINS 1 & DIGITAL OPERATING 24 XTAL, FILTER STANDARD DEFAULT XTALN ENABLED SDTV (Clean signals) 525 NTSC Yes 00 default 625 PAL Yes 00 ...
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Operation Summarized Table Default register settings. All with no external analog filter. No Mode setting. 525/625 (Continued) PINS 1 & DIGITAL OPERATING 24 XTAL, FILTER STANDARD DEFAULT XTALN ENABLED 1080 I / (29/30) Yes 00 default 1080 I / (48/50) ...
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Timing Diagram 5 - 720p Standard with Filter in Circuit Description of Operation The EL4511 has 3 modes of operation. The first is default mode with pins 1 and 24 connected to ground with 10K. Second is using pins 1 ...
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Video Format Switching The part should be powered down for at least 500µs to reset the internal registers when the input video signal is switched from one video format to another video format possible the part will generate ...
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Video Lock and Level Indicators Loss of video signal can be detected by monitoring the SYNCLOCK pin 3. This pin goes high once the sync separator has detected a valid sync signal and goes low if this signal is lost ...
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Application 2 (application using mode setting logic signals) In this example, the requirement is to provide the synchronizing information in a small display device. In this example the incoming sync signals may come from one of three sources. Computer, HDTV ...
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Serial Mode Operation See “Description of Operation” for more details of (Serial Mode). Using the Reference Oscillator and Counter A counter is provided for measuring the vertical time interval; this counts the clocks at the XTAL pin 1 between vertical ...
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TABLE 3. MODE CONTROL TRUTH TABLE (see also Table 2 for hardware over-ride) MODE EnTri EnBi EnHin TriLevel CTRL Level Level Vin Priority Reg ...
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TABLE 5. SERIAL INTERFACE REGISTER BIT ALLOCATIONS REGISTER REGISTER NUMBER BIT SIGNAL NAME 1 General Control Reg 1 7 General Reset 6 AlwaysEnOutputs 5:3 ModeCtrl 2 General Control Reg 2 5 Select Fixed Slicing (no S/H) 4 FILTER_ENABLED 1 OE_MODE ...
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TABLE 5. SERIAL INTERFACE REGISTER BIT ALLOCATIONS (Continued) REGISTER REGISTER NUMBER BIT SIGNAL NAME 7:6 CountsPerField <9:8> 5 SyncLock 4 CPFValid 3 SetBiLevel 2 VinSyncDet 1 VinPolarity 0 HPolarity 16 Oscillator Settings Observe 2 4 RateLocked 3 ALOS WRITE TO ...
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... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...