LMH0307GRE/NOPB National Semiconductor, LMH0307GRE/NOPB Datasheet - Page 10

• Manufacturer Part Number: LMH0307GRE/NOPB
• Description: IC CBL DVR DUAL HD/SD 25-UARRAY
• Manufacturer: National Semiconductor
• Type: Driverr

Specifications of LMH0307GRE/NOPB

• Applications: Amplifiers, Video Distribution
• Mounting Type: Surface Mount
• Package / Case: 25-Micro Array
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: LMH0307GRETR

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Address R/W Name
00h
01h
02h
R/W ID
R/W MASK
R
STATUS
Bits Field
7:1
7:5
0
4
3
2
1
0
7
6
5
4
3
2
1
0
DEVID
RSVD
RSVD
TF1N
TF1P
TF0N
TF0P
LOS
SD
PD1
PD0
MTF1N
MTF1P
MTF0N
MTF0P
MLOS
TABLE 1. SMBus Registers
0010111 Device ID. Writing this register will force the RSTO pin high.
Default Description
000
10
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Further accesses to the device must use this 7-bit address.
Reserved as 0. Always write 0 to this bit.
Reserved.
Termination Fault for SDI1.
0: No Termination Fault Detected.
1: Termination Fault Detected.
Termination Fault for SDI1.
0: No Termination Fault Detected.
1: Termination Fault Detected.
Termination Fault for SDI0.
0: No Termination Fault Detected.
1: Termination Fault Detected.
Termination Fault for SDI0.
0: No Termination Fault Detected.
1: Termination Fault Detected.
Loss Of Signal (LOS) detect at input.
0: No Signal Detected.
1: Signal Detected.
SD Rate select bit. If the SD/HD pin is set to V
this bit. With the SD/HD pin set to ground, this bit selects the
output edge rate as follows:
0: HD edge rate.
1: SD edge rate.
Power Down for SDO1 output stage. If the ENABLE pin is set
to ground, it overrides this bit. With the ENABLE pin set to
V
0: SDO1 active.
1: SDO1 powered down.
Power Down for SDO0 output stage. If the ENABLE pin is set
to ground, it overrides this bit. With the ENABLE pin set to
V
0: SDO0 active.
1: SDO0 powered down.
Mask TF1N from affecting FAULT pin.
0: TF1N=1 will cause FAULT to be 0.
1: TF1N=1 will not affect FAULT; the condition is masked off.
Mask TF1P from affecting FAULT pin.
0: TF1P=1 will cause FAULT to be 0.
1: TF1P=1 will not affect FAULT; the condition is masked off.
Mask TF0N from affecting FAULT pin.
0: TF0N=1 will cause FAULT to be 0.
1: TF0N=1 will not affect FAULT; the condition is masked off.
Mask TF0P from affecting FAULT pin.
0: TF0P=1 will cause FAULT to be 0.
1: TF0P=1 will not affect FAULT; the condition is masked off.
Mask LOS from affecting FAULT pin.
0: LOS=0 will cause FAULT to be 0.
1: LOS=0 will not affect FAULT; the condition is masked off.
CC
CC
, PD1 functions as follows:
, PD0 functions as follows:
CC
, it overrides