ISL59922IRZ Intersil, ISL59922IRZ Datasheet - Page 14

• Manufacturer Part Number: ISL59922IRZ
• Description: IC ANLG VID LINE TRPL 20-QFN
• Manufacturer: Intersil
• Type: Video Delay Liner

Specifications of ISL59922IRZ

• Applications: RGB Video Signals
• Mounting Type: Surface Mount
• Package / Case: 20-VQFN Exposed Pad, 20-HVQFN, 20-SQFN, 20-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

These steps are only necessary if the sync signal is
embedded on the video and you want to avoid possible
monitor blanking during skew adjustment.
Test Pins
Three test pins are provided (Test R, Test G, Test B). During
normal operation, the test pins output pulses of current for a
duration of the overlap between the inputs, as shown in
Figure 34:
TEST
TEST
TEST
Averaging the current gives a direct measure of the delay
between the two edges. When A precedes B, the current
pulse is +50µA, and the output voltage goes up. When B
precedes A, the pulse is -50µA.
For the logic to work correctly, A and B must have a period of
overlap while they are high (a delay longer than the pulse
width cannot be measured).
Signals A and B are derived from the video input by
comparing the video signal with a slicing level, which is set by
an internal DAC. This enables the delay to be measured
either from the rising edges of sync-like signals encoded on
top of the video or from a dedicated set-up signal. The outputs
can be used to set the correct delays for the signals received.
The DAC level is set through the serial input by bits 1
through 4 directed to the test register (00).
Internal DAC Voltage
The slice level of the internal DAC may be programmed by
writing a byte to the test register (00). Table 3 shows the
values that should be written to change the DAC slice level.
Please keep in mind when writing to the test register that the
LSB should always be zero.
Referred to the input, the DAC slice range for the ISL5992x
is cut in half for gain of 2 mode because the slicing occurs
after the x1/x2 stage output amplifier. (In the EL9115, the
slicing occurred before the amplifier so the range of the DAC
voltage was the same for either gain of 1 or gain of 2).
R
G
B
pulse = RED
pulse = BLUE
pulse = GREEN
OUT
OUT
OUT
(A) with respect to GREEN
with respect to RED
14
with respect to BLUE
ISL59920, ISL59921, ISL59922, ISL59923
OUT
OUT
OUT
(B)
NOTE: Test Register word = 000wxyz0. wxyz fed to DAC. z is LSB
TABLE 3. DAC VOLTAGE RANGE - INPUT REFERRED
GREEN
BLUE
000wxyz0
RED
wxyz
1000
1001
1010
0000
0001
0010
0100
0101
1011
1100
1101
0011
0110
1110
1111
0111
OUT
OUT
OUT
FIGURE 34. DELAY DETECTOR
OUTPUT
4
INTERNAL DAC
A
B
DAC RANGE [mV]
(GAIN 1)
-400
-350
-300
-250
-200
-150
-100
100
150
200
250
300
350
-50
50
0
SLICING LEVEL
A
B
COMPARATORS
A
B
A
B
DAC RANGE [mV]
(GAIN 2)
TEST
TEST
TEST
-200
-175
-150
-125
-100
100
125
150
175
August 31, 2010
-75
-50
-25
25
50
75
0
G
B
R
FN6826.2