LMH1983SQE/NOPB National Semiconductor, LMH1983SQE/NOPB Datasheet - Page 17

• Manufacturer Part Number: LMH1983SQE/NOPB
• Description: IC VID CLK GEN MULTI RATE 40LLP
• Manufacturer: National Semiconductor
• Type: Clock Generatorr

Specifications of LMH1983SQE/NOPB

• Applications: Video Equipment
• Mounting Type: Surface Mount
• Package / Case: 40-LLP
• Leaded Process Compatible: Yes
• Rohs Compliant: Yes
• Interface Type: I2C
• Supply Voltage (max): 3.3 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Peak Reflow Compatible (260 C): Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: LMH1983SQETR

ADD
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
Name
Loss of Reference
Threshold
Loss of Lock
Threshold
Mask Control – PLL
Lock and Output Align
Reserved
Reserved
Input Format
Output Frame Lookup
– Input Vsync Code
Bits
7
6:4
3
2:0
7:5
4:0
7
6
5
4
3
2
1
0
7:0
7:0
7:6
5:0
7:4
3:0
Field
RSVD
HSYNC_Missing
Threshold
RSVD
LOR_Threshold
RSVD
LOCK1_Threshold
MASK_LOCK4
MASK_LOCK3
MASK_LOCK2
MASK_LOCK1
MASK_TOF4_ALIG
N
MASK_TOF3_ALIG
N
MASK_TOF2_ALIG
N
MASK_TOF1_ALIG
N
RSVD
RSVD
RSVD
Input Format
RSVD
Input Vsync Code
17
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
00
001
10000
0
0
0
0
0
0
0
0
000000
0011
Description
Reserved
Sets the threshold for number of additional
clocks to wait before setting
HSYNC_Missing.
Reserved
Sets the number of Hsync periods to wait
before setting loss of reference. Since during
blanking there can have up to 5 missing
Hsync pulses, this value is usually set to 6.
Reserved
Sets the number of Hsync periods to wait
before setting loss of lock. Since during
blanking there can have up to 5 missing
Hsync pulses, this value is usually set > 6.
Setting this bit masks the PLL4 lock status in
the global LOCK_STATUS bit.
Setting this bit masks the PLL3 lock status in
the global LOCK_STATUS bit.
Setting this bit masks the PLL2 lock status in
the global LOCK_STATUS bit.
Setting this bit masks the PLL1 lock status in
the global LOCK_STATUS bit.
Setting this bit masks the TOF4 align status
in the global ALIGN_STATUS bit.
Setting this bit masks the TOF3 align status
in the global ALIGN_STATUS bit.
Setting this bit masks the TOF2 align status
in the global ALIGN_STATUS bit.
Setting this bit masks the TOF1 align status
in the global ALIGN_STATUS bit.
Reserved
Reserved
Reserved
When Auto Format Detection is enabled
(EN_AFD, address 0x05), this register is
read-only and controlled automatically.
When Auto Format Detection is disabled, this
register is writable via I
All writes to this register (whether automatic
or manual) will update all the LUT1 (Lookup
Table 1), LUT2_2, and LUT2_3 output
registers based on the value written here.
Writing to any of the LUT1, LUT2_2, or
LUT2_3 output registers will set this field to
6’d62 (0x3E) indicating that custom changes
have been made.
Reserved
Writes to this register update the Vsync code
which tells the device what the Input frame
rate is. There is a table which correlates the
Vsync codes to the actual frame rates. When
Auto Format Detection is enabled (EN_AFD,
address 5), this register is read-only, and is
automatically loaded by the device.
2
C.
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